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CMX7031/cmx7041 the two - way radio processor ? datasheet provisional issue 7031/7041 fi - 1.5 : baseband audio and data processor with auxiliary system clocks, adcs and dacs for use in analogue radio systems features ? co ncurrent audio/signalling/data o pera tions ? selectable audio processing order ? full audio - band processing: pre and de - emphasis, compandor, scrambler and selectable 2.55/3 .0 khz filters ? msk/ffsk data mo dem with packet or free - format m odes with fec, crc, interleaving and scrambling ? 2 x rf synth esisers (CMX7031 only) ? inband signalling: selcall, dtmf, noaa nwr ? 3 x analogue inputs (mic or discriminator) ? enhanced dsc modem for marine applications , offering support for dsc expansion sequences and transmission of continuous distress signals ? 2 x auxil iary adcs and 4 x auxiliary dacs ? sub - audio signalling: ctcss, dcs, xtcss ? c - bus serial interface to host controller ? low - power (3.0v to 3.6v) operation ? tx outputs for single, two - point or i/q mod. ? 559bps psk modulator ? available in 64 - pin, 48 - pin lqfp and vqfn packages ? 2 x auxiliary system clock outputs ? flexible powersave modes 1. brief description the CMX7031/cmx7041 fi 1. 5 is a full - function, half - duplex, audio, signalling and data process or ic. this makes it a suitable device for both the leisure radio markets (frs, murs, pmr446 and gmrs) and for professional radio products (pmr/lmr, marine and trunking) with or without signalling and data facilities. the device utilises cmls proprietary firmasic ? component technology. on - chip sub - systems are configured by a function image ? : this is a data file that is uploaded during device initialisation and defines the devices function and feature set. the function image ? can be loaded automatically fr om an external eeprom or from a host controller over the built - in c - bus serial interface. the devices functions and features can be enhanced by subsequent function image ? releases, facilitating in - the - field upgrades. this document refers specifically to the features provided by function image ? 1.5 . continued cml microcircuits communication semiconductors cmx 7031 / cmx 7041 the two - way radio processor modulator rf discriminator host c system clock 1 system clock 2 reference clock dac outputs adc inputs 3 . 0 v to 3 . 6 v built on firmasic ? technology gpio rf synthesiser 1 rf synthesiser 2 cmx 7031 only c - bus datasheet user manual this document contains :
the two - way radio processor CMX7031/cmx7041 ? the CMX7031 features two on - chip rf synthesisers, with easy rx/tx frequency changeover, and programmable system clocks to minimise chip count in the final application. the cmx7041 is identical in fu nctionality to the CMX7031 with the exception that the two on - chip rf synthesisers have been deleted, which enables it to be supplied in a smaller package and with two extra gpio pins. this document refers to both parts generically as the CMX7031, unless o therwise stated. when loaded with function image ? 1. 5 , both devices perform simultaneous processing of sub - audio and inband signalling and audio band processing (including frequency inversion scrambling, companding and pre - or de - emphasis). other features include a complete msk/ffsk modem for packetised or free - format data, a dsc modem, two auxiliary adc channels with four selectable inputs and up to four auxiliary dac interfaces (with an optional ramdac on the first dac output, to facilitate transmitter po wer ramping). the device has flexible powersaving modes and is available in both lqfp and vqfn packages. note that text shown in pale grey indicates features that will be supported in future versions of the device. this datasheet is the first part of a two - part document comprising datasheet and user manual: the user manual can be obtained by registering your interest in these products with your local cml representative.
the two - way radio processor CMX7031/cmx7041 ? contents section page 1. brief description ................................ ................................ ................................ ...................... 1 1.1. history ................................ ................................ ................................ ........................... 5 2. block diagram ................................ ................................ ................................ .......................... 8 3 . signal list ................................ ................................ ................................ ................................ . 9 3.1. signal definitions ................................ ................................ ................................ ........ 11 4. external components ................................ ................................ ................................ ............ 12 5. pcb layout guidelines and power supply decoupling ................................ .................... 15 6. general description ................................ ................................ ................................ ............... 17 7. detailed descriptions ................................ ................................ ................................ ............ 19 7.1. xtal frequency ................................ ................................ ................................ ............ 19 7.2. host interface ................................ ................................ ................................ ............. 19 7.2.1 c - bus operation ................................ ................................ ................................ . 19 7.3. function image ? load and activation ................................ ................................ ....... 21 7.3.1 fi loading from host controller ................................ ................................ ........... 22 7.3.2 fi loading from eeprom ................................ ................................ ................... 24 7.4. device control ................................ ................................ ................................ ............ 25 7.4.1 signal routing ................................ ................................ ................................ ...... 26 7.4.2 mode control ................................ ................................ ................................ ........ 27 7.5. audio functions ................................ ................................ ................................ .......... 28 7.5.1 audio receive mode ................................ ................................ ............................ 28 7.5.2 audio transmit mode ................................ ................................ ........................... 30 7.5.3 audio compandor ................................ ................................ ................................ 34 7.6. sub - audio signalling ................................ ................................ ................................ ... 36 7.6.1 receiving and decoding ctcss tones ................................ .............................. 36 7.6.2 receiving and decoding dcs codes ................................ ................................ .. 38 7.6.3 transmit ctcss tone ................................ ................................ ......................... 40 7.6.4 transmit dcs code ................................ ................................ ............................. 40 7.7. inband signalling C selcall/dtmf/user tones ................................ ........................... 41 7.7.1 receiving and decoding inband tones ................................ ............................... 41 7.7.2 receiving dtmf tones ................................ ................................ ....................... 42 7.7.3 transmitting inband tones ................................ ................................ .................. 42 7.7.4 transmitting dtmf tones ................................ ................................ ................... 42 7.7.5 alternative selcall tone sets ................................ ................................ ............... 43 7.8. xtcss signalling ................................ ................................ ................................ ....... 43 7.8.1 xtcss tx ................................ ................................ ................................ ............ 44 7.8.2 xtcss rx ................................ ................................ ................................ ............ 44 7.9. msk/ffsk data modem ................................ ................................ ............................ 44 7.9.1 receiving msk/ffsk signals ................................ ................................ .............. 45 7.9.2 transmitti ng msk/ffsk signals ................................ ................................ .......... 45 7.10. msk / ffsk data packetising ................................ ................................ ...................... 46 7.10.1 tx hang bit ................................ ................................ ................................ .......... 46 7.10.2 frame format ................................ ................................ ................................ ...... 46
the two - way radio processor CMX7031/cmx7041 ? 7.10.3 frame head ................................ ................................ ................................ ......... 47 7.10.4 data block coding ................................ ................................ ............................... 47 7.10.5 crc and fec encoding information ................................ ................................ ... 48 7.10.6 data interleaving ................................ ................................ ................................ .. 48 7.10.7 data scrambling/privacy co ding ................................ ................................ .......... 49 7.10.8 data buffer timing ................................ ................................ ............................... 49 7.11. fsk 1200bps dsc modem ................................ ................................ ........................ 50 7.11.1 receiving 1200 bps fsk (dsc) signals ................................ .............................. 51 7.11.2 transmitting 1200 bps fsk (dsc) signals ................................ .......................... 53 7.12. psk encoder ................................ ................................ ................................ .............. 54 7.13. noaa / nwr same and wat decoding ................................ ................................ ... 54 7.13.1 message code format ................................ ................................ ......................... 55 7.13.2 wat detection ................................ ................................ ................................ ..... 55 7.13.3 same decoding ................................ ................................ ................................ ... 55 7.14. auxiliary adc operation ................................ ................................ ............................. 56 7.15. auxiliary dac / ramdac operation ................................ ................................ ............ 57 7.16. rf synthesiser (CMX7031 only) ................................ ................................ ................ 57 7.17. digital system clock gene rators ................................ ................................ ................ 61 7.17.1 main clock operation ................................ ................................ ........................... 62 7.17.2 system clock operation ................................ ................................ ...................... 62 7.18. gpio ................................ ................................ ................................ ........................... 62 7.19. signal level optimisation ................................ ................................ ........................... 62 7.19.1 transmit path levels ................................ ................................ ........................... 63 7.19.2 receive path levels ................................ ................................ ............................. 63 7.20. c - bus register summary ................................ ................................ .......................... 64 7.20.1 interrupt operation ................................ ................................ ............................... 65 7.20.2 general notes ................................ ................................ ................................ ...... 65 8. performance specification ................................ ................................ ................................ ... 66 8.1. electrical pe rformance ................................ ................................ ............................... 66 8.1.1 absolute maximum ratings ................................ ................................ ................. 66 8.1.2 operating limits ................................ ................................ ................................ ... 67 8.1.3 operating characteristics ................................ ................................ ..................... 68 8.1.4 parametric performance ................................ ................................ ...................... 74 8.2. c - bus timing ................................ ................................ ................................ ............. 79 8.3. packaging ................................ ................................ ................................ ................... 80 table page table 1 definition of power supply and reference voltages ................................ ........................ 11 table 2 xtal/clock frequency settings for program block 3 ................................ ......................... 19 table 3 booten pin states ................................ ................................ ................................ ......... 21 tab le 4 ctcss irq conditions ................................ ................................ ................................ .... 37 table 5 ctcss tones ................................ ................................ ................................ .................. 38 table 6 dcs modulation modes ................................ ................................ ................................ ... 39 table 7 dcs 23 - bit codes ................................ ................................ ................................ ............ 40 table 8 inband tones ................................ ................................ ................................ ................... 42 table 9 dtmf tone pairs ................................ ................................ ................................ ............. 43 table 10 alternative selcall tone sets ................................ ................................ ......................... 43 table 11 data frequencies for each baud rate ................................ ................................ ........... 46
the two - way radio processor CMX7031/cmx7041 ? table 12 data block formatting types ................................ ................................ ......................... 48 table 13 maximum data transfer latency ................................ ................................ ................... 49 table 14 c - bus registers ................................ ................................ ................................ ............ 64 figure page figure 1 block diagram ................................ ................................ ................................ ................... 8 figure 2 CMX7031 recommended external components ................................ ........................... 12 figure 3 cmx7041 recommended external components ................................ ........................... 13 figure 4 CMX7031 power supply connections and de - coupling ................................ ................. 15 figure 5 cmx7041 power supply connections and de - coupling ................................ ................. 16 figure 6 c - bus transactions ................................ ................................ ................................ ....... 20 figure 7 fi loading from host ................................ ................................ ................................ ...... 23 figure 8 fi loading from eeprom ................................ ................................ .............................. 24 figure 9 signal routing ................................ ................................ ................................ ................. 26 figure 10 rx 12.5khz channel audio filter frequency response ................................ ............... 29 figure 11 rx 25khz channel audio filter frequency response ................................ .................. 29 figure 12 de - emphasis curve for tia/eia - 603 compliance ................................ ........................ 30 figure 13 tx channel audio filter response and template (etsi) ................................ ............. 31 figure 14 tx channel audio filter response and template (tia) ................................ ............... 32 figure 15 audio frequency pre - emphasis ................................ ................................ .................... 33 figure 16 expandor transient response ................................ ................................ ..................... 35 figure 17 compressor transient response ................................ ................................ ................. 35 figure 18 low pass sub - audio band filter for ctcss and dcs ................................ ................ 36 figure 19 modulating waveforms for 1200 and 2400 baud msk/ffsk signals .......................... 46 figure 20 dsc format ................................ ................................ ................................ .................. 50 figure 21 dsc character format ................................ ................................ ................................ . 51 figure 22 expanded dsc format ................................ ................................ ................................ . 52 figure 23 auxadc irq operation ................................ ................................ ................................ 56 figure 24 example rf synthesiser components for a 512mhz receiver ................................ ... 57 fig ure 25 single rf channel block diagram ................................ ................................ ............... 58 figure 26 digital clock generation schemes ................................ ................................ ............... 61 figure 27 level adjustments ................................ ................................ ................................ ......... 63 figure 28 c - bus timing ................................ ................................ ................................ ............... 79 figure 29 mechanical outline of 64 - pin vqfn (q1) ................................ ................................ ..... 80 figure 30 mechanical outline of 64 - pin lqfp (l9) ................................ ................................ ....... 80 figure 31 mechanical outline of 48 - pin vqfn (q3) ................................ ................................ ..... 81 figure 32 m echanical outline of 48 - pin lqfp (l4) ................................ ................................ ....... 81 1.1. history version changes date 13 ? ? ? ?
the two - way radio processor CMX7031/cmx7041 ? version changes date 11 ? c11, disc input cap acitor changed to 470nf to optimise ctcss/dcs decode timing. ? updated ctcss detection parametrics 17.10.11 10 ? correct rf synthesiser specification, following further evaluation 16.06.11 9 ? correct an error in the eeprom fi - loading flowchart and clarify the reset options available in sections 7.3 and 10.1. 27.04.11 8 section change 2, 3 and 4, etc revised usage of pin names, to coincide with other fis 3.1 addition of signal definitions section 4 clarification of vdec decoupling - note 8 5, 7.19 and 10.1 .27 clarification of usage of gain, attenuation and level terms 7.3 revised fi loading flowcharts, figs 7 and 8 7.10.4 identified the position of the rx frame sync pattern in the rx data 1 register. 7.20 and 10.1 revised and corrected the c - bus register table. table in section 10.1 is now hyperlinked. 8.1.3 corrected the range of the n divider (rf pll) 10.1.2 operation of general reset command clarified 10.1.9 definitions of fine and coarse adjustments clarified 10.1.11 corrected the range of the r d ivider (rf pll) 10.1.27 definition of audio tone register ($cd) clarified 10.2 programming register limit of p4.8 increased to p4.12 10.2.3 footnote added to definition of p2.0 various typographical corrections and clarifications 27.01.10 7 sect ion change 3 gpio1&2 defined as rx and tx enable c - bus signal names standardised adc signal names standardised 7.12 559bps encoder added 7.13 note that wat detector will re - arm after 500ms of tone fig 24 updated to latest version contact details updated 03.04.09 6 section change 7.9.1 added text on re - starting frame sync detection. 7.17 fi - 1.3.8.2 qualification for gpio a & b. fig 25 fi - 1.3.8.2 qualification. 8.1.3 power supply parametric updated. 8.1.4 note 75 corrected. note 76 add ed. dtmf levels corrected. residual hum & noise levels corrected. 26.01.09
the two - way radio processor CMX7031/cmx7041 ? version changes date 5 section change fig 1 text corrected on rf synth block 3 rxena and txena added to pin list table 7.5.1 text on inversion frequency added 7.5.2 extraneous the remove d more c - bus references added 7.6.1 note 8 clarified 7.17 rxena, txena description and reference to gpio a & b added figure 25 revised to show tx voice level multiplier table 3 ctcss irq states added 05.09.08 4 section change 3 note on metal pad added 7.1 settings for 9.0592 xtal replaced with 9.216mhz 7.2 note on c - bus latency added 7.2 additional text for irq operation added 7.3 pull - up resistors on booten pins changed to 220k 7.5.2 input agc section added 7.6.1 ctcss phase change detecti on corrected 7.13 auxadc threshold operation clarified and fig 21 added 7.14 auxdac output in powersave clarified 7.16.2 default states of sysclk1 & 2 defined for both CMX7031 and cmx7041 8.1.3 aux adc conversion time corrected 8.1.4 reference to p2.4 corrected to p2.5 in note 7 8.1.4 scrambler pass - band corrected fig 1 typos in block diagram corrected fig 2,3,4,5 components re - numbered, c4 removed fig 24 minimum clk input changed from 4mhz to 3mhz fig 26,27,28,29 package drawings updated 21.07. 08 2, 3 updates to reflect changes to the fi. jul 2007 sep 2007 1 original document. jan 2007 it is always recommended that you check for the latest product datasheet version from the cml website: [ www.cmlmicro. com ].
the two - way radio processor CMX7031/cmx7041 ? 2. block diagram figure 1 block diagram altfb discfb gpio 1 / txena gpio 2 / rxena gpioa gpiob in - band signalling transmit functions mod 1 audio mod 2 micn adc 1 adc 2 adc 3 adc 4 dac 1 epsclk b o o t e n 1 b o o t e n 2 epscsn output 2 output 1 sysclk 1 sysclk 2 dac 2 dac 3 dac 4 a v d d v b i a s a v s s x t a l / c l k x t a l n epso epsi auxiliary multiplexed adcs auxiliary dacs auxiliary system clocks system control internal signal tx mod mode audio processing analogue routing de - emphasis ( optional ) gpio fi configured i / o dac 1 dac 2 dac 3 dac 4 ramp profile ram mux adc 1 thresholds averaging thresholds averaging system clock 1 system clock 2 c - bus interface irqn rdata sclk power control registers eeprom interface bias d v d d v d e c d v s s reg crystal oscillator boot control main clock pll auxiliary functions receive functions adc 2 synthesiser 1 rf 1 p cp 1 out iset 1 synthesiser 2 rf 2 p cp 2 out iset 2 rfvdd cpvdd rfvss rfclk rf synthesisers ( cmx 7031 only ) gpio ( cmx 7041 only ) voice filter de - scrambler ( optional ) expander ( optional ) bpf mux rx modem rx data modem audio processing ffsk / msk marine dsc fsk nwr same free format flexible packet mux hpf dtmf two - tone paging selcall programmable tones mux lpf tone squelch signalling dcs xtcss ctcss cdata csn input 1 input 2 vbias mux mux pre - emphasi s ( optional ) soft limite r chann el filter scrambl er ( optiona l ) compress or ( optional ) tx modem tx data modem ffsk / msk marine dsc fsk free format flexible packet in - band signalling dtmf two - tone paging selcall programmable tones tone squelch signalling dcs xtcss ctcss mux mux vbias vbias voice filter micfb altn discn rf 1 n rf 2 n
the two - way radio processor CMX7031/cmx7041 ? 3. signal list CMX7031 64 - pin q1/l9 cmx7041 48 - pin q3/l4 pin name type description 1 8 irqn op c - bus: a 'wire - orable' output for connection to the interr upt request input of the host. pulled down to dv ss when active and is high impedance when inactive. an external pull - up resistor (r1) is required. 2 - rf1n ip rf synthesiser #1 negative input. 3 - rf1p ip rf synthesiser #1 positive input. 4 - rfvss pw r the negative supply rail (ground) for the 1st rf synthesiser. 5 - cp1out op 1st charge pump output. 6 - iset1 ip 1st charge pump current set input. 7 - rfvdd pwr the 2.5v positive supply rail for the rf synthesisers. this should be decoupled to rfv ss by a capacitor mounted close to the device pins. 8 - rf2n ip rf synthesiser #2 negative input. 9 - rf2p ip rf synthesiser #2 positive input. 10 - rfvss pwr the negative supply rail (ground) for the 2nd rf synthesiser. 11 - cp2out op 2nd charge pump out put. 12 - iset2 ip 2nd charge pump current set input. 13 - cpvdd pwr the 3.3v positive supply rail for the rf charge pumps. this should be decoupled to rfv ss by a capacitor mounted close to the device pins. 14 - rfclk ip rf clock input (common to both s ynthesisers) 1 . 15 - - nc reserved C do not connect this pin. 16 - - nc reserved C do not connect this pin. 17 - - nc reserved C do not connect this pin. 18 9 vdec pwr internally generated 2.5v digital supply voltage. must be decoupled to dv ss by capaci tors mounted close to the device pins. no other connections allowed, except for optional connection to rfv dd . 19 10 rxena op rx enable C active low when in rx mode ($c1:b0 = 1) - 11 gpioa op general purpose i/o pin (cmx7041 only) - 12 gpiob op general purpose i/o pin (cmx7041 only) 20 13 sysclk1 op synthesised digital system clock output 1. 21 14 dvss pwr digital ground. 22 - - nc reserved C do not connect this pin. 23 15 txena op tx enable C active low when in tx mode ($c1:b1 = 1) 24 16 discn ip c hannel 1 inverting input. 25 17 discfb op channel 1 input amplifier feedback. 1 to minimise crosstalk, this signal should be connected to the same clock source as xtal/clock input.
the two - way radio processor CMX7031/cmx7041 ? CMX7031 64 - pin q1/l9 cmx7041 48 - pin q3/l4 pin name type description 26 18 altn ip channel 2 inverting input. 27 19 altfb op channel 2 input amplifier feedback. 28 20 micfb op channel 3 input amplifier feedback. 29 21 micn ip channel 3 invert ing input. 30 22 avss pwr analog ground. 31 23 mod1 op modulator 1 output. 32 24 mod2 op modulator 2 output. 33 25 vbias op internally generated bias voltage of about av dd /2, except when the device is in powersave mode when vbias will discharge to av ss . must be decoupled to av ss by a capacitor mounted close to the device pins. no other connections allowed. 34 26 audio op audio output. 35 27 adc1 ip auxiliary adc input (1) each of the two adc blocks can select its input signal from any one of these input pins, or from the mic, alt or disc input pins. see section 9.1.3 for details 36 28 adc2 ip auxiliary adc input (2) 37 29 adc3 ip auxiliary adc input (3) 38 30 adc4 ip auxiliary adc input (4) 39 31 avdd pwr positive 3.3v supply rail for the analogue on - chip circuits. levels and thresholds within the device are proportional to this voltage. this pin should be decoupled to av ss by capacitors mounted close to the device pins. 40 32 dac1 op auxiliary dac output 1/ramda c. 41 33 dac2 op auxiliary dac output 2. 42 34 avss pwr analogue ground. 43 35 dac3 op auxiliary dac output 3. 44 36 dac4 op auxiliary dac output 4. - 37 dvss pwr digital ground. 45 38 vdec pwr internally generated 2.5v supply voltage. must be decoup led to dv ss by capacitors mounted close to the device pins. no other connections allowed, except for the optional connection to rfv dd . 46 39 xtal/clk ip input to the oscillator inverter from the xtal circuit or external clock source. 47 40 xtaln op the o utput of the on - chip xtal oscillator inverter. 48 41 dvdd pwr the 3.3v positive supply rail for the digital on - chip circuits. this pin should be decoupled to dvss by capacitors mounted close to the device pins. 49 42 cdata ip c - bus: serial data input fr om the c. 50 43 rdata ts op c - bus: a 3 - state c - bus serial data output to the c. this output is high impedance when not sending data to the c. 51 44 - nc reserved C do not connect this pin.
the two - way radio processor CMX7031/cmx7041 ? CMX7031 64 - pin q1/l9 cmx7041 48 - pin q3/l4 pin name type description 52 45 dvss pwr digital ground. 53 - - nc reserved C do not c onnect this pin. 54 46 sclk ip c - bus: the c - bus serial clock input from the c. 55 47 sysclk2 op synthesised digital system clock output 2. 56 48 csn ip c - bus: the c - bus chip select input from the c - there is no internal pullup on this input. 57 - - nc reserved C do not connect this pin. 58 1 epsi op eeprom serial interface: spi bus output. 59 2 epsclk op eeprom serial interface: spi bus clock. 60 3 epso ip+pd eeprom serial interface: spi bus input. 61 4 epscsn op eeprom serial interface: spi bus chip select. 62 5 booten1 ip+pd used in conjunction with booten2 to determine the operation of the bootstrap program. 63 6 booten2 ip+pd used in conjunction with booten1 to determine the operation of the bootstrap program. 64 7 dvss pwr digital ground. e xposed m etal p ad e xposed m etal p ad substrate ~ on this device, the central metal pad (which is exposed on q1 & q3 packages only) may be electrically unconnected or, alternatively, may be connected to analogue ground (avss). no other electrical connectio n is permitted. notes: ip = input (+ pu/pd = internal pullup / pulldown resistor) op = output bi = bidirectional ts op = 3 - state output pwr = power connection nc = no connection - should not be connected to any signal. 3.1. signal definitions table 1 definition of power supply and reference voltages signal name pins usage av dd avdd power supply for analogue circuits dv dd dvdd power supply for digital circuits rfv dd rfvdd power supply for rf synthesiser circuits cpv dd cpvdd power supply for rf charge pump v dec vdec power supply for core logic, derived from dv dd by on - chip regulator v bias vbias internal analogue reference level, derived from av dd av ss avss ground for all analogue circuits dv ss dvss ground for all digital c ircuits rfv ss rfvss ground for all rf circuits
the two - way radio processor CMX7031/cmx7041 ? 4. external components figure 2 CMX7031 recommended external components
the two - way radio processor CMX7031/cmx7041 ? figure 3 cmx7041 recommended external components
the two - way radio processor CMX7031/cmx7041 ? r1 100k ? c1 18pf c11 see note 5 c21 10nf r2 100k ? c2 18pf c12 100pf c22 10nf r3 100k ? c3 10nf c13 see note 5 c23 10nf r4 100k ? c4 not used c14 100pf c24 10f r5 see note 2 c5 1nf c15 see note 5 c25 10nf r6 100k ? c6 100pf c16 180pf c26 10f r7 see note 3 c7 1 00nf c17 10f c27 10nf r8 100k ? c8 100pf c18 10nf c28 10f r9 see note 4 c9 100pf c19 10nf x1 6.144mhz r10 100k ? c10 not used c20 10f see note 1 resistors ? 5%, capacitors and inductors ? 20% unless otherwise stated. notes: 1. x1 can be a cryst al or an external clock generator; this w ill depend on the application. the tracks between the crystal and the device pins should be as short as possible to achieve maximum stability and best start up performance. by default, a 6.144mhz crystal is assumed, other values could be used if the various internal clock dividers are set to appropriate values. 2. r5 should be selected to provide the desired dc gain (assuming c11 is not present) of the discriminator input, as follows: ? gain disc ? = 100k ? / r5 the gain sh ould be such that the resultant output at the discfb pin is within the discriminator input signal range specified in 7.19.2 . 3. r7 should be selected to provide the desired dc gain (assuming c13 is not present) of the alternative input as follows: ? gain alt ? = 100k ? / r7 the gain should be such that the resultant output at the altfb pin is within the alternative input signal range specified in 7.19 . 4. r9 should be selected to provide the desired dc gain (a ssuming c15 is not present) of the microphone input as follows: ? gain mic ? = 100k ? / r9 the gain should be such that the resultant output at the micfb pin is within the microphone input signal range specified in 7.19.1 . for opti mum performance with low signal microphones, an additional external gain stage may be required. 5. c11, c13 and c15 should be selected to maintain the lower frequency roll - off of the microphone, alternative and discriminator inputs as follows: c11 ? 470nf ? ? gain disc ? c13 ? 1.0f ? ? gain alt ? c15 ? 30nf ? ? gain mic ? c11 should be chosen to optimise the frequency and response times of the ctcss/dcs decoders. some applications may require this capacitor to be increased to 1f. 6. alt and altfb connections allow the user to have a second disc riminator or microphone input. component connections and values are as for the respective disc and mic networks. if this input is not required, the alt pin should be connected to avss. 7. c5 (audio out) should be increased to 1.0f if frequencies below 300hz need to be used on this pin. 8. a single 10f electrolytic capacitor (c24, fitted as shown) may be used for smoothing the power supply to both vdec pins, providing they are connected together on the pcb with an adequate width power supply trace. alternatively, separate smoothing capacitors should be connected to each vdec pin. high frequency decoupling capacitors (c3 and c23) must always be fitted as close as possible to both vdec pins.
the two - way radio processor CMX7031/cmx7041 ? 5. pcb layout guidelines and power supply decoupl ing figure 4 CMX7031 power supply connections and de - coupling
the two - way radio processor CMX7031/cmx7041 ? figure 5 cmx7041 power supply connections and de - coupling component values as per figure 2 . notes: it is impo rtant to protect the analogue pins from extraneous inband noise and to minimise the impedance between the device and the supply and bias de - coupling capacitors. the de - coupling capacitors c3, c7, c18, c19, c21, c22, c24 and c25 should be as close as possib le to the device. it is therefore recommended that the printed circuit board is laid out with separate ground planes for the av ss , rfv ss and dv ss supplies in the area of the CMX7031, with provision to make links between them, close to the device. use of a multi - layer printed circuit board will facilitate the provision of ground planes on separate layers. v bias is used as an internal reference for detecting and generating the various analogue signals. it must be carefully decoupled, to ensure its integrity, so apart from the decoupling capacitor shown, no other loads should be connected. if v bias needs to be used to set the discriminator mid - point reference, it must be buffered with a high input impedance buffer. the single ended microphone input and audio o utput must be ac coupled (as shown), so that their return paths can be connected to av ss without introducing dc offsets. further buffering of the audio output is advised. the crystal x1 may be replaced with an external clock source. the 2.5v v dec output ca n be used to supply the 2.5v rfv dd , to remove the need for an external 2.5v regulated supply. v dec can be directly connected to rfv dd , in which case c23 should be omitted.
the two - way radio processor CMX7031/cmx7041 ? 6. general description the CMX7031/cmx7041 are intended for use in half duplex analog ue two way mobile radio or family radio equipment and is particularly suited to both the pmr / marine markets and enhanced murs / gmrs / frs with gps terminal designs. the CMX7031/cmx7041 provide radio signal encoder and decoder functions for: audio, inband tone s, dtmf, xtcss , ctcss, dcs and msk/ffsk /fsk data, permitting simple to sophisticated levels of tone control and data transfer. a flexible power control facility allows the device to be placed in its optimum powersave mode when not actively processing signa ls. the CMX7031/cmx7041 include a crystal clock generator, with buffered output, to provide a common system clock if required. a block diagram of the CMX7031/cmx7041 is shown in figure 1 . the signal processing blocks can be indiv idually assigned to either of two signal processing paths, which in turn, can be routed from any of the three audio / discriminator input pins. this allows for a very flexible routing architecture and allows the facility for different processing blocks to ac t on different analogue inputs. eg: ctcss may be processed from the disc input, while selcall can be processed from the alt input in parallel. for marine use, it would be typical to route rx audio from the working channel receiver through from the disc inp ut, while at the same time routing the dsc fsk modem from the dsc channel 70 receiver from the alt input. tx functions: o single/dual microphone inputs with input amplifier and programmable gain adjustment o filtering selectable for 12.5khz and 25khz channels o selectable pre - emphasis o selectable compression o selectable frequency inversion voice scrambling o selectable audio processing order o 2 - point modulation outputs with programmable level adjustment o i/q modulation outputs with programmable level adjustment o pre - pro grammed 51 tone ctcss encoder o 120/180 degree ctcss phase shift generation o programmable 23/24bit dcs encoder o programmable selcall generator o programmable audio tone generator (for custom audio tones) o programmable dtmf generator o pre - programmed xtcss and inban d tone encoder o 1200/2400 baud msk / ffsk modem and data packet encoder (suitable for text messaging/paging, caller identification, caller location, digital poll of remote radio location, gps information in nmea 0183 format, data transfer, mpt1327 etc.) incor porating interleaving, fec, crc and data scrambler o 1200bps fsk modem for dsc use (to itu - r m.493 - 11) . also offers support for enhanced dsc function s (support for dsc expansion sequences and transmission of continuous distress signals) o 559bps psk modem o tx e nable output rx functions: o single/dual demodulator inputs with input amplifier and programmable gain adjustment o audio - band and sub - audio rejection filtering o selectable de - emphasis o selectable expansion o selectable frequency inversion voice de - scrambling o sel ectable audio processing order o software volume control o 1 from 51 ctcss decoder + tone clone ? mode o 120/180 degree ctcss phase shift detection o 23/24bit dcs decoder o selcall decoder o dtmf decoder
the two - way radio processor CMX7031/cmx7041 ? o pre - programmed inband tone decode with xtcss 4 - tone addressing o 12 00/2400 baud msk / ffsk data packet decoder with automatic bit rate recognition, 16 bit frame sync detector, error correction, data de - scrambler and packet disassembly o 1200bps fsk modem for dsc use (to itu - r m.493 - 11) . also offers support for enhanced dsc fu nction s (support for dsc expansion sequences and transmission of continuous distress signals) o nwr same and wat detector o rx enable output auxiliary functions: o 2 flexible integer - n rf synthesisers (CMX7031 only) o 2 programmable system clock outputs o 2 auxilia ry adcs with selectable input paths o 4 auxiliary dacs, one with built - in programmable ramdac interface: o c - bus, 4 wire high speed synchronous serial command / data bus o open drain irq to host o 2 gpio pins (cmx7041 only) o eeprom boot mode o c - bus boot mode o spi - code c (only available when fi is loaded into cmx7131/cmx 7141 devices)
the two - way radio processor CMX7031/cmx7041 ? 7. detailed descriptions 7.1. xtal frequency the CMX7031/cmx7041 are designed to work with a xtal or external frequency source of 6.144mhz. if this default configuration is not used, then program register block 3 (see user manual 9.2.4 ) needs to be loaded with the correct values to ensure that the device will work to specification with the user specified clock frequency. a table of common values can be found in table 2 . note the maximum xtal frequency is 12.288mhz, although an external clock source of up to 24.576mhz can be used. the register values in table 2 are shown in hex (however only the lower 10 bits are releva nt), the default settings are shown in bold, and the settings which do not give an exact setting (but are within acceptable limits) are in italics. the new p3.2 - 3 settings take effect following the write to p3.3 (the settings in p3.4 - 7 are implemented on a change to rx or tx mode). table 2 xtal/clock frequency s ettings for program block 3 program register external frequency source (mhz) 3.579 6.144 9.216 12.0 12.8 16.368 16.8 19.2 p3.2 idle gp timer $017 $018 $018 $019 $019 $01 8 $019 $018 p3.3 vco output and aux clk divide $085 $088 $08c $10f $110 $095 $115 $099 p3.4 rx or tx ref clk divide $043 $040 $060 $07d $0c8 $155 $15e $0c8 p3.5 pll clk divide $398 $200 $200 $200 $300 $400 $400 $200 p3.6 vco outp ut and aux clk divi de $140 $140 $140 $140 $140 $140 $140 $140 p3.7 internal adc/dac clk divide $008 $008 $008 $008 $008 $008 $008 $008 note that if the spi - codec routing is used in rx mode on a cmx7131/cmx7141 then this value will need to be changed from $140 to $0c0 . 7.2. host interface a serial data interface (c - bus) is used for command, status and data transfers between the CMX7031/cmx7041 and the host c; this interface is compatible with microwire, spi. interrupt signals notify the host c when a change in status has occurred and the c should read the status register across the c - bus and respond accordingly. interrupts only occur if the appropriate mask bit has been set. see section 7.20.1 . the CMX7031/cmx7041 will monitor the state of the c - bus registers that the host has written to every 250s (the c - bus latency period) hence it is not advisable for the host to make successive writes to the same c - bus register within this period. to minimise ac tivity on the c - bus interface, optimise response times and ensure reliable data transfers, it is advised that the irq facility be utilised (using the irq mask register, $ce). it is permissible for the host to poll the irq pin if the host uc does not suppor t a fully interrupt - driven architecture. this removes the need to continually poll the c - bus status register ($c6) for status changes. 7.2.1 c - bus operation this block provides for the transfer of data and control or status information between the CMX7031/cmx704 1s internal registers and the host c over the c - bus serial interface. each transaction consists of a single address byte sent from the c which may be followed by one or more data byte(s) sent from the c to be written into one of the CMX7031/cmx7041s w rite only registers, or one or more data byte(s) read out from one of the CMX7031/cmx7041s read on ly registers, illustrated in figure 6 .
the two - way radio processor CMX7031/cmx7041 ? data sent from the c on the cdata line is clocked into the CMX7031/cmx7041 on the rising ed ge of the sclk clock input. rdata sent from the CMX7031/cmx7041 to the c is valid when the sclk is high. the csn line must be held low during a data transfer and kept high between transfers. the c - bus interface is compatible with most common c serial in terfaces and may also be easily implemented with general purpose c i/o pins controlled by a simple software routine. the number of data bytes following an address byte is dependent on the value of the address byte. the most significant bit of the address or data are sent first. for detailed timings see section 8.2 . note that, due to internal timing constraints, there maybe a delay of up to 250s between the end of a c - bus write operation and the device reading the data from it s internal register. c - bus write: see note 1 see note 2 csn sclk cdata 7 6 5 4 3 2 1 0 7 6 0 7 0 msb lsb msb lsb msb lsb address/com mand byte upper 8 bits lower 8 bits rdata high z state c - bus read: see note 2 csn sclk cdata 7 6 5 4 3 2 1 0 msb lsb address byte upper 8 bits lower 8 bits rdata 7 6 0 7 0 high z state msb lsb msb lsb data value unimportant repeated c ycles either logic level valid (and may change) either logic level valid (but must not change from low to high) figure 6 c - bus transactions notes: 1. for command byte transfers only the first 8 bits are transferred ($01 = reset). 2. for single byte data transfers only the first 8 bits of the data are transferred. 3. the cdata and redata lines are never active at the same time. the address byte determines the data direction for each c - bus transfer. 4. the sclk input can be high or l ow at the start and end of each c - bus transaction. 5. the gaps shown between each byte on the cdata and rdata lines in the above diagram are optional, the host may insert gaps or concatenate the data as required.
the two - way radio processor CMX7031/cmx7041 ? 7.3. function image ? load and activation the funct ion image ?(fi) file, which defines the operational capabilities of the device, may be obtained from the cmltechnical portal, following product registration. this is in the form of a c header file which can be included into the host controller software o r programmed into an external eeprom. the maximum possible size of function image? is 46 kbytes, although a typical fi will be less than this. note that the booten pins are only read at power - on or following a c - bus general reset and must remain stable t hroughout the fi loading process. once the fi load has completed, the booten pins are ignored by the CMX7031/cmx7041 until the next power - up or c - bus general reset. the booten pins are both fitted with internal low - current pulldown devices. for c - bus lo ad operation, both pins should be pulled high by connecting them to v dd either directly or via a 220k resistor (see table 3 ). for eeprom load, only booten1 needs to be pulled high in a similar manner, however, if it is required to program the eeprom in - situ from the host, either a jumper to v dd or a link to a host i/o pin should be provided to pull booten2 high when required (see table 3 ). once the fi has been loaded, the CMX7031/cmx7041 performs these actions: (1) the product identification code $7031 is reported in c - b us register $c5 (2) the fi version code is reported in c - bus register $c9 (3) the two 32 - bit fi checksums are reported in c - bus register pairs $a9, $aa and $b8, $b9 (4) the device waits for the host to load the 32 - bit device activation code to c - bus reg ister $c8 (5) once activated, the device initialises fully, enters idle mode and becomes ready for use, and the programming flag (bit 0 of the status register, $c6) will be set. the checksums should be verified against the published values to ensure that the fi has loaded correctly. once the fi has been activated, the checksum, product identification and version code registers are cleared and these values are no longer available. if an invalid activation code is loaded, the device will report the value $ dead in register $a9 and become unresponsive to all further host commands (including general reset). a power - on reset is required to recover from this state. both the device activation code and the checksum values are available from the cml technical port al. table 3 booten p in s tates booten2 booten1 c - bus host load 1 1 reserved 1 0 eeprom load 0 1 no fi load 0 0 note: in the rare event that a general reset needs to be issued without the requirement to re - load the fi, the bo oten pins must both be cleared to '0' before issuing the reset command. the checksum values will be reported and the device activation code will need to be sent in a similar manner as that shown in figure 8 . there will not be any fi loading delay. this assumes that a valid fi has been previously loaded and that v dd has been maintained throughout the reset to preserve the data.
the two - way radio processor CMX7031/cmx7041 ? 7.3.1 fi l oading from host controller the fi can be included into the host controller softwar e build and downloaded into the CMX7031/cmx7041 at power - up over the c - bus interface. the booten pins must be set to the c - bus load configuration, the CMX7031/cmx7041 powered up and placed into program mode, the data can then be sent directly over the c - bu s to the CMX7031/cmx7041 . each time the device is powered up its function image ? must first be loaded and then activated. these two steps assign internal device resources and determine all device features. the device does not operate until the function i mage ? is loaded and activated.
the two - way radio processor CMX7031/cmx7041 ? figure 7 fi l oading from host the download time is limited by the clock frequency of the c - bus, with a 5mhz sclk, it should take less than 500ms to complete. booten 2 = 1 booten 1 = 1 power - up or write general reset to cmx 7031 / cmx 7041 poll $ c 6 until b 0 = 1 ( prg flag set ) configure prg flag interrupt , if required write $ 0001 to $ c 8 write start block 1 address ( db 1 _ ptr ) to $ b 6 write block 1 length ( db 1 _ len ) to $ b 7 wait for prg flag to go high or interrupt write next data word to $ c 8 wait for prg flag to go high or interrupt write start block 2 address ( db 2 _ ptr ) to $ b 6 write block 2 length ( db 2 _ len ) to $ b 7 write $ 0001 to $ c 8 wait for prg flag to go high or interrupt wait for prg flag to go high or interrupt write next data word to $ c 8 write start block 3 address ( activate _ ptr ) to $ b 6 write block 3 length ( activate _ len ) to $ b 7 write $ 0001 to $ c 8 wait for prg flag to go high or interrupt send activation code hi to $ c 8 read and verify checksum values in register pair : $ a 9 and $ aa , $ b 8 and $ b 9 send activation code lo to $ c 8 wait for prg flag to go high or interrupt wait for prg flag to go high or interrupt booten 1 and booten 2 may be changed from this point on , if required cmx 7031 / cmx 7041 is now ready for use booten 1 booten 2 v dd
the two - way radio processor CMX7031/cmx7041 ? 7.3.2 fi l oading from eeprom the fi must be converted into a format for the eeprom programmer (normally intel hex) and loaded into the eeprom either by the host or an external programmer. the CMX7031/cmx7041 needs to have the booten pins set to eeprom load, and then on power - on, or following a c - bus general reset, the CMX7031/cmx7041 will automatically load the data from the eeprom without intervention from the host controller. figure 8 fi l oading from eeprom the CMX7031/cmx7041 has been designed to function with atmel at25hp512 serial eeprom and the at25f512 flash eeprom devices 2 , however other manufacturers parts may also be suitable. the time taken to load the fi is dependant on the xtal frequency, with a 6.144mhz xtal, it should load in less than 1 second. 2 note that these two devices have slightly different addressing schemes. fi 1.5 is compatible with both scheme s, whereas previous fi s were only compatible with the at25hp512 addressing scheme. booten 2 = 0 booten 1 = 1 power - up or write general reset to cmx 7031 / cmx 7041 poll $ c 6 until b 0 = 1 ( prg flag set ) configure prg flag interrupt if required send activation code hi to $ c 8 read and verify checksum values in register pair : $ a 9 and $ aa , $ b 8 and $ b 9 send activation code lo to $ c 8 wait for prg flag to go high or interrupt wait for prg flag to go high or interrupt booten 1 and booten 2 may be changed from this point on , if required cmx 7031 / cmx 7041 is now ready for use booten 1 booten 2 v dd jumper for programming eeprom ( if required )
the two - way radio processor CMX7031/cmx7041 ? 7.4. device control the CMX7031/cmx7041 can be set into many modes to suit the environment in which it is to be used. these modes are described in the fo llowing sections and are programmed over the c - bus: either directly to operational registers or, for parameters that are not likely to change during operation, via the programming register ($c8). for basic operation: 1. enable the relevant hardware sections v ia the power down control register 2. set the appropriate mode registers to the desired state (audio, inband, sub - audio, data etc.), 3. select the required signal routing and gain 4. use the mode control register to place the device into rx or tx mode. note that when the device changes from idle mode to either tx or rx, the mod or audio outputs may exhibit a momentary spike as the output stages become active. this can be negated by selecting the appropriate output routing path a short time (approx. 1ms) after ch anging mode. to conserve power when the device is not actively processing an analogue signal, place the device into idle mode. additional powersaving can be achieved by disabling the unused hardware blocks, however, care must be taken not to disturb any s ections that are automatically controlled. see: o power down control C $c0 write o mode control C $c1 write
the two - way radio processor CMX7031/cmx7041 ? 7.4.1 signal routing the CMX7031/cmx7041 offers a very flexible routing architecture, with three signal inputs, two separate signal processing paths and a selection of two modulator outputs (to suit 2 - point as well as i/q modulation schemes) and a single audio output. each of the signalling processing blocks can be independently routed to either of the input blocks, which can be routed to any of the three input signal pins. the audio / voice processing blocks are always routed to input 1. the outputs from signal processing blocks are determined by the settings of the auxadc and tx mod mode register in tx mode. see: o input gain and output signal routing C $b1 write o auxadc and tx mod mode C $a7 write o mode control C $c1 write note: spi - codec routing is only a vailable when this function image ? is loaded into the cmx7131/cmx7141. figure 9 signal routing the analogue gain / attenuation of each input and output can be set individually, with additional fine gain control available via the pr ogramming registers and the audio tone register. flexible packet ffsk / msk / fsk modem ctcss tone squech signalling lpf dcs xtcss bpf data modem in - band signalling programmable tone selcall dtmf two - tone paging de - emphasis expander de - scrambler channel filter audio processing receive functions alt i / p mic i / p disc i / p vbias mux $ c 1 b 7 hpf mux $ c 1 b 11 hpf audio routing $ b 1 b 6 vbias vbias input 2 $ b 1 b 15 - 13 input 1 $ b 1 b 12 - 10 free format mux $ c 1 b 4 mux $ b 1 b 3 , 2 mux $ b 1 b 5 , 4 audio gain $ b 0 b 3 - 0 data modem compressor scrambler inband signalling selcall programmable tone two - tone paging dtmf tone squelch signalling ctcss xtcss dcs audio processing transmit functions pre - emphasis channel filtering soft limiter tx mod mode $ a 7 b 12 , 13 mux $ c 1 b 15 , 6 , 5 mux $ c 1 b 14 - 2 free format ffsk / msk / fsk modem output 1 output 2 flexible packet mod 2 gain $ b 0 b 10 - 8 mod 1 gain $ b 0 b 14 - 11 mux $ b 1 b 9 , 8 mux $ b 1 b 7 output 1 mux $ c 1 b 13 bpf modem nwr modem spi $ b 0 : b 5 nc $ b 0 : b 6 nc
the two - way radio processor CMX7031/cmx7041 ? see: o analogue output gain C $b0 write o input gain and output signal routing C $b1 write o audio tone C $cd: 16 - bit write - only addi tionally, on the cmx7131 and cmx7141 only, the input1 or output1 signals may be intercepted and routed to the full - duplex spi port , where they are presented and received as 16 - bit signed pcm values sampled at 8ksps , to allow for external processing of th ese signals . this port is shared with the serial memory, but uses the ssout pin as the chip select signal. by default, this function is disabled. there is no independent spi port on the CMX7031 or cmx7041, so this intercept routing is not available. see: o analogue output gain C $b0 write 7.4.2 mode control the CMX7031/cmx7041 operates in one of three modes: o idle o rx o tx at power - on or following a reset, the device will automatically enter idle mode, which allows for the maximum powersavi ng whilst still retaining the capability of monitoring the auxadc inputs (if enabled). it is only possible to write to the programming register whilst in idle mode. see: o mode control C $c1 write
the two - way radio processor CMX7031/cmx7041 ? 7.5. audio functions the audio signal can be processed in several ways, depending on the implementation required, by selecting the relevant bits in the audio control C $c2 write register. in both rx and tx, a selectable channel filter to suit either the 12.5khz or 25 khz tia / etsi channel mask can be selected. this filter also incorporates a soft limiter to reduce the effects of over - modulation. other features include 300hz hpf, pre - and de - emphasis, companding and frequency inversion scrambling, all of which may be ind ividually enabled 3 . the order in which these features are executed is selectable to ensure compatibility with existing implementations and provide optimal performance (see user manual section 9.2. 5 ). the default configuration i s backwards compatible with the CMX7031/7041 fi - 1.2 implementation, however the alternate settings shown in the user manual section 9.2.5 may provide better performance. 7.5.1 audio receive mode the CMX7031/cmx7041 operates in half d uplex, so whilst in receive mode the transmit path (microphone input and modulator output amplifiers) can be disabled and powered down if required. the audio output signal level is equalised (to v bias ) before switching between the audio port and the modul ator ports, to minimise unwanted audible transients. the off/powersave level of the modulator outputs is the same as the v bias pin, so the audio output level must also be at this level before switching. see: o audio control C $c2 write receiving audio band signals when a voice - based signal is being received, it is up to the host c, in response to signal status information provided by the CMX7031/cmx7041 , to control muting/enabling of the audio signal to the audio output. the discrim inator path through the device has a programmable gain stage. whilst in receive mode this should normally be set to 0db (the default) gain. receive filtering the incoming signal is filtered, as shown in figur e 10 (with the 300hz h pf also active), to remove sub - audio components and to minimise high frequency noise. when appropriate, the audio signal can then be routed to the audio output. separate selectable filters are available for: ? 300hz high pass (to reject sub - audible signalli ng) ? 2.55khz low pass (for 12.5khz channel operation) ? 3.0khz low pass (for 25khz channel operation) note that with no filters selected, the low frequency response extends to below 5hz at the low end but still rolls off above 3.3khz at the top end. 3 the typical responses shown in figur e 10 , figure 12 , figure 13 and figure 14 were recorded using the pe0201 evkit, disc in to audio and mod1 out.
the two - way radio processor CMX7031/cmx7041 ? figur e 10 rx 12.5khz channel audio filter frequency response figure 11 rx 25khz channel audio filter frequency response
the two - way radio processor CMX7031/cmx7041 ? figure 12 de - emphasis curve for tia/eia - 603 compliance de - emphasis optional de - emphasis at - 6db per octave from 300hz to 3000hz (shown in figure 12 ) can be selected, to facilitate compliance with tia/eia - 603, en 300 086, en 301 025 etc. the template shows the +1, - 3db l imits. rx companding (expanding) the CMX7031/cmx7041 incorporates an optional syllabic compandor in both transmit and receive modes. this expands received audio band signals that have been similarly compressed in the transmitter to enhance dynamic range. s ee section 7.5.3 and: o audio control C $c2 write audio de - scrambling the CMX7031/cmx7041 incorporates an optional frequency inversion de - scrambler in receive mode. this de - scrambles received audio band signals that have been scrambled in the transmitter. the inversion frequency defaults to 3300hz, but may be modified by writing to p4.8. see: o audio control C $c2 write 7.5.2 audio transmit mode the device operates in half duplex, so whe n the device is in transmit mode the receive path (discriminator and audio output amplifiers) should be disabled, and can be powered down, by the host c. two modulator outputs with independently programmable gains are provided to facilitate single or two - point modulation, separate sub - audio and audio band outputs. if one of the modulator outputs is not used it can be disabled to conserve power. to avoid spurious transmissions when changing from rx to tx the mod 1 and mod 2 outputs are ramped to the quiesc ent modulator output level, v bias before switching (if enabled by b7 of the analogue gain register, $b0). similarly, when starting a transmission, the transmitted signal is ramped up from the
the two - way radio processor CMX7031/cmx7041 ? quiescent v bias level and when ending a transmission the transmi tted signal is ramped down to the quiescent v bias level. the ramp rates are set in the programming register p4.6. when the modulator outputs are disabled, their outputs will be set to v bias . when the modulator output drivers are powered down, their outpu ts will be floating (high impedance), so the rf modulator will need to be turned off. for all transmissions, the host c must only enable signals after the appropriate data and settings for those signals are loaded into the c - bus registers. as soon as any signalling is enabled the CMX7031/cmx7041 will use the settings to control the way information is transmitted. a programmable gain stage in the microphone input path facilitates a host controlled vogad capability, or an internal agc function may be used. see: o audio control C $c2 write o auxadc and tx mod mode C $a7 write o input gain and output signal routing C $b1 write processing audio signals for transmission over analogue channe ls the microphone input(s), with programmable gain, can be selected as the audio input source. pre - emphasis is selectable with either of the two analogue tx audio filters (for 12.5khz and 25khz channel spacing). these are designed for use in en 300 086, tia/eia - 603 or en 301 025 compliant applications. when the 300hz hpf is enabled, it will attenuate sub - audio frequencies below 250hz by more than 33db with respect to the signal level at 1khz. these filters, together with a built in limiter, help ensure co mpliance with en 300 086 and en 301 025 (25khz and 12.5khz channel spacing) when levels and gain settings are set up correctly in the target system. figure 13 tx channel audio filter response and template (etsi) 250 250 3000 3000 2550 2550 300 300 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 10 1000 db (ref 1khz) frequency (hz) tx all filters off - $0000 hpf & 12.5k filter - $1400 template 25k filter - $0800
the two - way radio processor CMX7031/cmx7041 ? figure 14 tx channel audio filter response and template (tia) the characteristics of the 12.5khz channel filter fit the template shown in figure 13 and figure 14 . this filter also facilitate s implementation of systems compliant with tia/eia - 603 a , b and c bands. the CMX7031/cmx7041 provides selectable pre - emphasis filtering of +6db per octave from 300hz to 3000hz, matching the template shown in fi gure 15 . 250 250 3000 3000 2550 2550 300 300 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 10 1000 db (ref 1khz) frequency (hz) tx all filters off - $0000 hpf & 12.5k filter - $1400 template 25k filter - $0800
the two - way radio processor CMX7031/cmx7041 ? fi gure 15 audio frequency pre - emphasis modulator output routing the sub - audio component can be combined with the audio band signal and this composite signal routed to both mod1 and mod2 outputs, or the sub - audio and audio band sign al can be output separately (sub - audio to mod2 and audio band to mod1), in accordance with the settings of: o auxadc and tx mod mode C $a7 write o input gain and output signal routing C $b1 write alternative ly, the combined sub - audio and audio band composite signal can be output on mod1 and 2 in a phase/quadrature (i/q) format suitable for direct upconversion to the final rf signal. due to the nature of the i/q modulation, this mode is only feasible in rf cha nnels/systems which have a maximum frequency deviation of 3khz or less. additional test modes are provided for calibrating external circuits. tx i/q mode is particularly suitable for data transmission. input agc an automatic gain control system can be ena bled by setting the relevant bits of the program register p4.9. the setting of the input 1 gain stage is recorded when the device enters tx mode and if the signal exceeds the pre - set threshold, the input 1 gain is automatically reduced in 3.2db steps until it falls within the operational levels or the range of the gain stage is exhausted. when the signal level drops, the gain will be automatically increased in 3.2db steps at the rate set in p4.9 until the initial value has been reached. for maximum effect t he system should be designed such that the +22.4db setting of the input 1 gain stage achieves the nominal levels. to ensure consistent operation, it is recommended that the input 1 gain stage value be re - initialised before entering tx mode. the signal that is used as an input to this process can be selected to be either: o output of input 1 gain stage o output of the pre - emphasis filter
the two - way radio processor CMX7031/cmx7041 ? by selecting the relevant bit in p4.9. the pre - emphasis option should only be chosen if this block is actually in use. o input gain and output signal routing C $b1 write o program block 4 C gain and offset setup: tx companding (compressing) the CMX7031/cmx7041 incorporates an optional syllabic compandor in both trans mit and receive mode. this compresses audio band signals before transmission to enhance dynamic range. see section 7.5.3 and: o audio control C $c2 write audio scrambling the CMX7031/cmx7041 incorporates an optional frequency inversion scrambler in transmit mode. this scrambles audio band signals, to be de - scrambled in the receiver. the inversion frequency defaults to 3300hz, but maybe modified by writing to p4.8. see: o audio control C $c2 write 7.5.3 audio compandor the compandor is comprised of a compressor and an expandor. the compressors function is to reduce the dynamic range of a given signal by attenuating larger amplitudes while amplifying smaller amplitudes. the expandors fun ction is to expand the dynamic range of a given signal by attenuating small amplitude signals (e.g. noise) while amplifying large amplitude signals. the compressor is used prior to transmission and the expandor is used in the receiver. hence, using a compa ndor will enhance performance in a communication system by transmitting a compressed signal, which is less likely to be corrupted by noise, and then at the receiver expanding the compressed signal, which will push the noise picked up during transmission do wn further. the CMX7031/cmx7041 uses a syllabic compandor. this type of compandor, as opposed to the instantaneous compandor (e.g. /a - law pcm), responds to changes in the average envelope of the signal amplitude according to a syllabic time constant ? . typically the steady state output for the compressor is proportional to the square root of the input signal. ie:, for a 2 db change in input signal, the output change will be 1 db. generally for voice communication systems a compressor is expected to have an input dynamic range of 60 db, providing an output dynamic range of 30 db. the expandor does the inverse.
the two - way radio processor CMX7031/cmx7041 ? figure 16 expandor transient response figure 17 compressor transient response
the two - way radio processor CMX7031/cmx7041 ? 7.6. sub - aud io signalling sub - audio signalling is available in the audio band below 260hz. when sub - audio signalling is enabled, the 300hz hpf in the audio section should also be enabled to remove the sub - audio signalling from the audio signal (in both tx and rx). bot h ctcss tones and dcs codes are supported, as well as a special tone - cloning mode which will report back any received ctcss tone rather than look for a specific tone. there are 51 ctcss tones defined in the CMX7031/cmx7041 and there is provision for a us er - specified tone. tone inversion to implement reverse tone burst for squelch tail elimination can be accomplished by inverting the output of the mod1 and mod2 outputs ($b0) or by using the phase change facility in the audio control register ($c2). the d cs coder / decoder supports both 23 - and 24 - bit modes with both true and inverse modulation formats and the 134hz end of transmission burst. the ctcss tone and dcs code values for both rx and tx operation are specified in the audio control register ($c2), in the lowest 8 bits (shown in decimal): o 0 no tone o 1 to 83 dcs code 1 to 83 o 84 user - defined dcs code o 101 to 183 inverted dcs code 1 to 83 o 184 inverted user - defined dcs code o 200 ctcss tone clone ? mode o 201 to 254 ctcss tones 1 to 51, user, xtcss and dcsoff tones o 255 invalid tone the ctcss and dcs functions are enabled by the relevant bits in the mode control register, $c1, so that the host can turn the functionality on or off without having to re - program the values in the audio control register , $c2. see: o analogue output gain C $b0 write o mode control C $c1 write o audio control C $c2 write 7.6.1 receiving and decoding ctcss tones the CMX7031/cmx7041 is able to accurately dete ct valid ctcss tones quickly to avoid losing the beginning of audio or data transmissions, and is able to continuously monitor the detected tone with minimal probability of falsely dropping out. the received signal is filtered in accordance with the templ ate shown in figure 18 , to prevent signals outside the sub - audio range from interfering with the sub - audio tone detection. figure 18 low pass sub - audio band filter for ctcss and dcs -70 -60 -50 -40 -30 -20 -10 0 10 0 200 400 600 800 1000 frequency (hz) gain (db)
the two - way radio processor CMX7031/cmx7041 ? once a valid ctcss t one has been detected, status register ($c6) b11 will be set and the host c can then route the audio band signal to the audio output. the audio band signal is extracted from the received signal by band pass filtering as shown in figur e 10 . to optimise the ctcss tone decoder, adjustable decoder bandwidths and threshold levels allow the user to trade - off decode certainty against signal to noise performance when congestion or range restrict the system performance. the tone decoder b andwidth and threshold level are set in p2.1 of the programming register ($c8) and the desired tone is programmed in the audio control register ($c2). in systems which make use of tones 41 to 50 or other split tones (tones in between the frequencies of t ones 1 to 40), the ctcss decoder bandwidth should be reduced to avoid false detection of adjacent tones. the CMX7031/cmx7041 includes a ctcss tone phase detector which reacts to a phase change in the received tone of +/ - 90 degrees by setting bit 9 of the tone status register ($cc) and asserting b11 of the status register ($c6). this feature can be used to detect both 180 and 120 degree phase changes and so allow the host to mute the audio appropriately (squelch tail elimination). tone cloning ? tone cloning ? facilitates the detection of ctcss tones 1 to 39 in receive mode which allows the device to non - predictively detect any tone in this range. this mode is activated by programming ctcss tone number 00 (b0 - 7 of audio control = 200 decimal). the received ton e number will be reported in the tone status register and can then be programmed into the audio control register by the host c. the cloned tone will only be active when ctcss is enable d in the mode control register. this setting has no effect in tx mode a nd the ctcss generator will output no signal. tone cloning ? should not be used in systems where tones 41 to 51 or other split tones (tones between the frequencies of tones 1 to 40) may be received. the all - call tone 40 can still be used after tone clonin g has been performed. the ctcss decoder detection bandwidth should be set to its lowest value (in p2.1 of the programming register) to ensure accurate detection. ctcss tones table 5 lists the ctcss tones available, the tone number s and the equivalent (decimal) values that need to be programmed into the audio control register ($c2) and which will be reported back in the tone status register ($cc). if enabled, an irq will be generated under the following conditions: table 4 ctcss irq c onditions state change from: to: irq tone status value b7 - 0 no tone own tone yes own tone own tone no tone yes $00 no tone unrecognised tone yes $ff unrecognised tone no tone yes $00 no tone invalid tone yes $ff or detected tone invalid tone no tone yes $00 t tone cloning ? is a trademark of cml microsystems plc.
the two - way radio processor CMX7031/cmx7041 ? table 5 ctcss tones register v alue tone register v alue tone register v alue tone dec hex no. freq (hz) dec hex no. freq(hz) dec hex no. freq (hz) 000 00 n/a no tone 218 da 18 123.0 237 ed 37 2 41.8 200 c8 0 toneclone 219 db 19 127.3 238 ee 38 250.3 201 c9 1 67.0 220 dc 20 131.8 239 ef 39 69.3 202 ca 2 71.9 221 dd 21 136.5 240 f0 40 62.5 203 cb 3 74.4 222 de 22 141.3 241 f1 41 159.8 204 cc 4 77.0 223 df 23 146.2 242 f2 42 165.5 205 cd 5 79. 7 224 e0 24 151.4 243 f3 43 171.3 206 ce 6 82.5 225 e1 25 156.7 244 f4 44 177.3 207 cf 7 85.4 226 e2 26 162.2 245 f5 45 183.5 208 d0 8 88.5 227 e3 27 167.9 246 f6 46 189.9 209 d1 9 91.5 228 e4 28 173.8 247 f7 47 196.6 210 d2 10 94.8 229 e5 29 179.9 24 8 f8 48 199.5 211 d3 11 97.4 230 e6 30 186.2 249 f9 49 206.5 212 d4 12 100.0 231 e7 31 192.8 250 fa 50 229.1 213 d5 13 103.5 232 e8 32 203.5 251 fb 51 254.1 214 d6 14 107.2 233 e9 33 210.7 252 fc 52 user 215 d7 15 110.9 234 ea 34 218.1 253 fd 53 xtcss 216 d8 16 114.8 235 eb 35 225.7 254 fe 54 dcsoff 217 d9 17 118.8 236 ec 36 233.6 255 ff 55 invalid notes: 1. register value 000 in b0 - 7 of the tone status register ($cc) indicates that none of the above sub - audio tones is being detected. if register val ue 000 is programmed into the audio control register ($c2) and ctcss enabled in the mode control register ($c1), only ctcss tone 40 (240 decimal) will be scanned for. if ctcss transmit is selected, this tone setting will cause the ctcss generator to outpu t no signal. 2. tone number 40 (240 decimal) provides an all - user ctcss tone option; regardless of the sub - audio tones set, the CMX7031/cmx7041 will report the presence of this tone whenever the ctcss detector is enabled. this feature is useful for implement ing emergency type calls e.g. all - call. 3. tone number 55 (255 decimal) is reported in the tone status register ($cc), when ctcss receive is enabled and a sub - audio tone is detected that does not correspond to the selected tone or the all - call tone (tone numb er 40). this could be a tone in the sub - audio band which is not in the table or a tone in the table which is not the selected tone or all - call tone. 4. tones 40 to 51 (241 to 251 decimal) are not in the tia - 603 standard. 5. tone number 52 (252 decimal) will sele ct the user programmable tone value in program block 2 C ctcss and dcs setup: 6. tone number 53 (253 decimal) will select the xtcss call maintenance tone, 64.7hz 7. tone number 54 (254 decimal) will select the dcs turn - off tone, 134.4hz . 8. tone clone, register value 200, is a write - only value to $c2. the received tone number will be reported back in $cc. 7.6.2 receiving and decoding dcs codes dcs code is in nrz format and transmitted at 134.4 ? 0.4bps. the CMX7031/cmx7041 is able to decode any 23 - or 24 - bit pattern in either of the two dcs modulation modes defined by tia/eia - 603 and described in t able 6 . the CMX7031/cmx7041 can detect a valid dcs code quickly enough to avoid losing the beginning of audio transmissions.
the two - way radio processor CMX7031/cmx7041 ? t able 6 dcs modulation modes modulation type: data bit: fm frequency change: a 0 negative frequency shift 1 positive frequency shift b 0 positive frequency shift 1 negative frequency shift the CMX7031/cmx7041 detects the dcs code that matches the programmed code defined in the audio control register ($c2) in either its true or inverted form. register values 1 to 83 correspond to modulation type a (true) and register values 101 to 183 correspond to modulation type b (inverte d). a facility for a user - defined code is available via program block 2 C ctcss and dcs setup: to detect the pre - programmed dcs code, the signal is low - pass filtered to suppress all but the sub - audio band, using the filter shown in figure 18 . further equalisation filtering, signal slicing and level detection are performed to extract the code being received. the extracted code is then matched with the programmed 23 - or 24 - bit dcs code to be recognised, in the order least significant first through to most significant dcs code bit last. table 7 shows a selection of valid 23 - bit dcs codes: this does not preclude other codes being programmed. recognition of a valid dcs code will be f lagged if the decode is successful (3 or less errors) by setting b10 of the status register ($c6) to 1. a failure to decode is indicated by clearing this bit to 0. this bit is updated after the decoding of every 4th bit of the incoming signal. the actual code received is reported back in the tone status register ($cc) according to table 7 , so that the host c can determine if it was the true or inverted form of the code. once a valid dcs code has been detected, the host c can rout e the audio band signal to the audio output. the audio signal is extracted from the received input signal by band pass filtering, see figur e 10 . the end of dcs transmissions is indicated by a 134.4 ? 0.5hz tone for 150 - 200ms. when a valid dcs code has been detected, the CMX7031/cmx7041 will automatically scan for the turn - off tone. when a dcs turn off tone is detected it will cause a dcs interrupt and report tone 54 (tone status b0 - 7 value 254 decimal); the receiver audio output ca n then be muted by the host. note that dcs detection and ctcss detection cannot be performed concurrently.
the two - way radio processor CMX7031/cmx7041 ? table 7 dcs 23 - b it codes reg value true reg value invert dcs code dcs bits 22 - 12 dcs bits 11 - 0 reg value true reg value invert dcs code dcs bits 22 - 12 dcs bits 11 - 0 reg value true reg value invert dcs code dcs bits 22 - 12 dcs bits 11 - 0 1 101 023 763 813 29 129 174 18b 87c 57 157 445 7b8 925 2 102 025 6b7 815 30 130 205 6e9 885 58 158 464 27e 934 3 103 026 65d 816 31 131 223 68e 893 59 159 465 60b 935 4 104 031 5 1f 819 32 132 226 7b0 896 60 160 466 6e1 936 5 105 032 5f5 81a 33 133 243 45b 8a3 61 161 503 3c6 943 6 106 043 5b6 823 34 134 244 1fa 8a4 62 162 506 2f8 946 7 107 047 0fd 827 35 135 245 58f 8a5 63 163 516 41b 94e 8 108 051 7ca 829 36 136 251 627 8a9 64 164 532 0e3 95a 9 109 054 6f4 82c 37 137 261 177 8b1 65 165 546 19e 966 10 110 065 5d1 835 38 138 263 5e8 8b3 66 166 565 0c7 975 11 111 071 679 839 39 139 265 43c 8b5 67 167 606 5d9 986 12 112 072 693 83a 40 140 271 794 8b9 68 168 612 671 98a 13 113 073 2e6 83b 41 141 306 0cf 8c6 69 169 624 0f5 994 14 114 074 747 83c 42 142 311 38d 8c9 70 170 627 01f 997 15 115 114 35e 84c 43 143 315 6c6 8cd 71 171 631 728 999 16 116 1 15 72b 84d 44 144 331 23e 8d9 72 172 632 7c2 99a 17 117 116 7c1 84e 45 145 343 297 8e3 73 173 654 4c3 9ac 18 118 125 07b 855 46 146 346 3a9 8e6 74 174 662 247 9b2 19 119 131 3d3 859 47 147 351 0eb 8e9 75 175 664 393 9b4 20 120 132 339 85a 48 148 364 685 8f4 76 176 703 22b 9c3 21 121 134 2ed 85c 49 149 365 2f0 8f5 77 177 712 0bd 9ca 22 122 143 37a 863 50 150 371 158 8f9 78 178 723 398 9d3 23 123 152 1ec 86a 51 151 411 776 909 79 179 731 1e4 9d9 24 124 155 44d 86d 52 152 412 79c 90a 80 180 732 10e 9da 25 125 156 4a7 86e 53 153 413 3e9 90b 81 181 734 0da 9dc 26 126 162 6bc 872 54 154 423 4b9 913 82 182 743 14d 9e3 27 127 165 31d 875 55 155 431 6c5 919 83 183 754 20f 9ec 28 128 172 05f 87a 56 156 432 62f 91a 84 184 user defined notes: 1. register value 84 will select the user programmable dcs code value in program block 2 C ctcss and dcs setup: register value 184 will select the inverted form of the user progr ammable dcs code. 2. note that the audio control register values are shown in decimal. 7.6.3 transmit ctcss tone the sub - audio ctcss tone generated is defined in the audio control register ($c2). table 5 lists the ctcss tones and the corre sponding decimal values for pr ogramming b0 - 7 of the register. to facilitate squelch tail elimination and reverse tone burst, the phase of the transmitted tone can be altered by either 120, 180 or 240 degrees by setting b9, b8 in the audio control register ($c2). the phase change is not instantaneous, but implemented by retarding the phase of the tone to its new value over a number of cycles to avoid the generation of spurious signals. a 180 degree change will be completed within 20ms. 7.6.4 transmit dcs code a 23 - or 24 - bit sub - audio dcs code can be generated, as defined by the audio control register ($c2). the same dcs code pattern is used for detection and transmission. the dcs code is nrz encoded at 134.4 ? 0.4 bps, low - pass filtered and added to the audio band s ignal, before being passed to the modulator output stages. valid 23 - bit dcs codes and the corresponding settings for the audio control register are shown in table 7 , and include a user - defined facility. the least significant bit of the dcs code is transmitted first and the most significant bit is transmitted last. the CMX7031/cmx7041 is able to encode
the two - way radio processor CMX7031/cmx7041 ? and transmit either of the two dcs modulation modes defined by tia/eia - 603 (true and inverted) described in t able 6 . if 24 - bit mode is required, bit 11 of programming register p2.1 should be set. to signal the end of the dcs transmission, the host should set the audio control register ($c2) to the dcs turn off tone (register value b0 - 7 = 254 decimal) for 150ms to 200ms. after this time period has elapsed the host should then disable dcs in the mode control register ($c1). 7.7. inband signalling C selcall/dtmf/user tones the cm7031 supports both selcall, dtmf and user - programmable inband tones between 288hz and 3000 hz. note that if tones below 400hz are used, sub - audio signalling should be disabled and the 300hz hpf disabled. by default, the CMX7031/cmx7041 will load the eea selcall tone set, however this may be over - written by the host with any valid set of tones wi thin its operational range by use of the programming register. this ensures that the device can remain compatible with all available tone systems in use. the CMX7031/cmx7041 does not implement automatic repeat tone insertion or deletion: it is up to the ho st to correctly implement the appropriate selcall protocol. selection of the inband signalling mode is performed by bits 11 - 9 of the mode register ($c1). detection of the selected inband signalling mode can be performed in parallel with audio or data recep tion. see: o mode control C $c1 write o tx inband tones C $c3 write o tone status C $cc read 7.7.1 receiving and decoding inband tones inband tones can be used to flag the start of a call or to confirm the end of a call. if they occur during a call the tone may be audible at the receiver. when enabled, an interrupt will be issued when a signal matching a valid inband tone changes state (ie: on, off or a change to different tone). the CMX7031/ cmx7041 implements qtc coding using the eea tone set. other addressing and data formats can be implemented by loading the programming registers with the appropriate values. the custom tones (1 - 4) permit other audio tones to be encoded or decoded. the frequ ency of each tone is defined in the programming registers p1.18 to p1.21. in receive mode the CMX7031/cmx7041 scans through the tone table sequentially. the code reported will be the first one that matches the incoming frequency and b13 of the irq status r egister, $c6, will be asserted. adjustable decoder bandwidths and threshold levels are programmable via the programming register. these allow certainty of detection to be traded against signal to noise performance when congestion or range limits the system performance. the inband signal is derived from the received input signal after the band pass filtering shown in figur e 10 .
the two - way radio processor CMX7031/cmx7041 ? table 8 inband tones custom tones: (b15 = 0) selcall tones: (b15 = 1) b14 - 1 1 freq. b14 - 11 freq. dec hex (hz) dec hex (hz) 0 0 no tone 0 0 1981 (p1.2) 1 1 custom tone 1 p1.18 1 1 1 1124 (p1.3) 2 2 custom tone 2 p1.19 1 2 2 1197 (p1.4) 3 3 custom tone 3 p1.20 1 3 3 1275 (p1.5) 4 4 custom tone 4 p1.21 1 4 4 1358 (p1.6) 5 5 5 5 1446 (p1.7) 6 6 6 6 1540 (p1.8) 7 7 7 7 1640 (p1.9) 8 8 8 8 1747 (p1.10) 9 9 9 9 1860 (p1.11) 10 a reserved 10 a 1055 (p1.12) 11 b 11 b 930 (p1.13) 12 c 12 c 2247 (p1.14) 13 d 13 d 991 (p1.15) 14 e 14 e 2110 2 (p1.16) 15 f unrecognised tone 15 f 2400 (p1.17) notes: 1 custom tones 1 - 4 provide user programmable tone options for both transmit and receive modes as set in the indicated program register, for programming information see section 9.2.2 in the CMX7031/cmx7041 user manual. 2 normally, tone 14 is the repeat tone. this code must be used in transmit mode when the new code to be sent is the same as the previous one. e.g. to send 333 the sequence 3r3 should be sent, where r is the repeat tone. when receiving selcall tones, the CMX7031/cmx7041 will indicate the repeat tone when it is received. it is up to the host to interpret and decode the tones accordingly. 7.7.2 receiving dtmf tones dtmf tone detection may be enabled in the mod e register ($c1) in parallel with other inband tone modes (however, this is not recommended due to the increased likelihood of false detects). when a dtmf tone has been detected, b10 of the tone status register ($cc) and b12 of the irq status register, $c6 , will be set. this value will over - write any existing inband tone value that may be present. the dtmf detector returns the values shown below in table 9 . 7.7.3 transmitting inband tones the inband tone to be generated is defined in the tx tone register ($c3). the tone level is set in the programming register (p1.0). the inband tone must be transmitted without other signals in the audio band, so the host c must disable the audio or data paths prior to initiating transmission of an inban d tone and restore them after the inband tone transmission is complete. table 8 shows valid inband tones, together with the values for programming the inband bits of the tx inband tones register. custom inband ton e frequencies are set in p1.18 - 21 of the programming register ($c8). see section 9.2.2 in the CMX7031/cmx7041 user manual for programming details. 7.7.4 transmitting dtmf tones the dtmf signals to be generated are def ined in the tx tone register ($c3). single tones and twist (lower frequency tone reduced by 2db) can be enabled by setting the appropriate bit in the $c3 register to '1'. the dtmf level is set in programming register p1.0. the dtmf tones must be transmi tted on their own, the host c must disable audio band signals prior to initiating transmission of the dtmf tones and (if required) restore the audio band signals after the dtmf transmission is complete. table 9 s hows the dtmf tone pairs, together with the values for programming the tone pair field of the tx tone register.
the two - way radio processor CMX7031/cmx7041 ? table 9 dtmf tone pairs tone code (hex) key pad position low tone (hz) high tone (hz) 1 1 697 1209 2 2 697 1336 3 3 697 1477 4 4 770 1209 5 5 770 1336 6 6 770 1477 7 7 852 1209 8 8 852 1336 9 9 852 1477 a 0 941 1336 b * 941 1209 c # 941 1477 d a 697 1633 e b 770 1633 f c 852 1633 0 d 941 1633 note: only the underlined tone is generated when the 'sing le tone' bit is enabled. 7.7.5 alternative selcall tone sets these may be loaded via the programming register to locations p1.2 to p1.17. see section 9.2.2 in the CMX7031/cmx7041 user manual . table 10 altern ative selcall tone sets frequency (hz) tone number eia eea ccir zvei 1 zvei 2 (p1.2) 0 600 1981 1981 2400 2400 (p1.3) 1 741 1124 1124 1060 1060 (p1.4) 2 882 1197 1197 1160 1160 (p1.5) 3 1023 1275 1275 1270 1270 (p1.6) 4 1164 1358 1358 1400 1400 (p1 .7) 5 1305 1446 1446 1530 1530 (p1.8) 6 1446 1540 1540 1670 1670 (p1.9) 7 1587 1640 1640 1830 1830 (p1.10) 8 1728 1747 1747 2000 2000 (p1.11) 9 1869 1860 1860 2200 2200 (p1.12) a (10) 2151 1055 2400 2800 885 (p1.13) b (11) 2435 930 930 810 810 (p1.1 4) c (12) 2010 2247 2247 970 740 (p1.15) d (13) 2295 991 991 885 680 (p1.16) e (14) 459 2110 2110 2600 970 (p1.17) f (15) notone 2400 1055 680 2600 7.8. xtcss signalling xtcss signalling combines the capabilities of the ctcss and selcall signalling systems described earlier to provide a simple address/format protocol. xtcss is used to identify the start and, optionally, the end of voice/data/other call. it provides additional information and control over the basic ctcss method of channel coding. xtcss codin g starts with a 4 - tone sequence indicating the address and co ntent of the following message. immediately after the 4 - tone sequence an optional sub - audio maintenance tone may be sent for the
the two - way radio processor CMX7031/cmx7041 ? duration of the call. at the end of the call the maintenance tone is removed and an optional 4 - tone sequence is sent, indicating the end of message (eom). see: o modem rx address C $b6 write o mode control C $c1 write o audio control C $c2 write o status C $c6 read o rx data 1 and 2 / xtcss C $c5 and $c9 read o tx data 1 and 2 / xtcss C $ca and cb write 7.8.1 xtcss tx the first two tones of the 4 - tone sequence represent the address of the r adio to be called and are loaded into the modem address register ($b6). the following two tones are steering digits which indicate the type of communication (voice, scrambled voice, data etc.) that follow s. these are loaded into the tx data 2 register ($ cb). the device will transmit the 4 tones in sequence, raise an interrupt when this is complete and then automatically generate the xtcss maintenance tone (if enabled). at the end of the message the maintenance tone is disabled by clearing the xtcss maint enance tone setting in th e audio control register ($c2). 7.8.2 xtcss rx by enabling xtcss reception the host instructs the CMX7031/cmx7041 to search for a valid 4 - tone sequ ence. an interrupt (if enabled) will be generated when this occurs. the 4 - tone sequence wi ll be indicated in the c - bus register ($c9) for the host to read out using the tone numbers in table 8 . to be valid, the 4 tones must be preceded and followed by silence in the audio band (signals below the audio d etect level - see program register p1.1) for the programmed no - tone time if enabled, by setting the xtcss maintenance tone setting in the audio control register ($c2), the sub - audio tone will be searched for after a valid 4 - tone inband sequence. the state of the sub - audio maintenance tone will only be indicated to the host if ctcss detection is also enabled. after the 4 - tone sequence is detected the maintenance tone can be used by the host to detect fades and the end of the message and hence can disable th e audio path as required. the CMX7031/cmx7041 will automatically search for the 4 - tone set whenever the xtcss enable bit is set and maintenance tone is not decoded. it is possible (although unlikely) that a fade will exactly coincide and obliterate 2 lots of 4 - tone sequences indicating an eom and the start of a new message. in this case, the host could misinterpret the received signal as a long fade and enable the voice when the maintenance tone reappears. it is therefore recommended that the host operate s a timer that is started on loss of maintenance tone. if this times out, the host can then assume that the fade is long enough that the original call is lost or has become so corrupted that it is not worth continuing with. the host can then choose to res tore the audio path on the next occurrence of a valid xtcss tone set. note that the xtcss detector operates independently and the host may enable or disable the audio path at any time. 7.9. msk/ffsk data modem the CMX7031/cmx7041 supports both 1200 and 2400 b ps msk/ffsk data modes (see section 7.11 for details of the 1200 bps fsk mode suitable for use in the marine vhf band for digital selective calling (dsc) to itu - r m.493 - 11 and section 7.12 for a 559 bps psk encoder). in rx mode, the device can be set to look for either of the msk or ffsk modes, however, once a valid mode has been found, it will stay in that mode un til the host resets it. see: o mode control C $c1 write o modem control C $c7 write o rx data 1 and 2 / xtcss C $c5 and $c9 read o tx data 1 and 2 / xtcss C $ca and cb write
the two - way radio processor CMX7031/cmx7041 ? 7.9.1 receiving msk/ffsk signals the CMX7031/cmx7041 can decode incoming msk/ffsk s ignals at either 1200 or 2400 baud data rates, automatically detecting the rate from th e received signal. alternatively, a control word may set the baud rate, in which case the device only responds to signals operating at that rate. the form of msk/ffsk si gnals for these baud rates is shown in figure 19 . the received signal is filtered and data is extracted with the aid of a pll to recover the clock from the serial data stream. the recovered data is stored in a 2 - or 4 - byte buffer ( grouped into 16 - bit words) and an interrupt issued to indicate received data is ready. data is transferred over the c - bus under host c control. if this data is not read before the next data is decoded it will be overwritten and it is up to the user to en sure that the data is transferred at an adequate rate following data ready being flagged, see table 13 . the msk/ffsk bit clock is not output externally. the extracted data is compared with the 16 - bit programmed frame sync pattern (preset to $cb23 following a reset command). an interrupt will be flagged when the programmed frame sync pattern is detected or when the following frame head is decoded, see section 7.10.3 . the host c may stop the frame sync s earch by disabling the msk/ffsk demodulator. once a valid frame sync pattern has been detected, the frame sync search algorithm is disabled; it may be re - started by the host disabling the modem control bits of the mode register ($c1:b2,3) and then re - enabl ing them (taking note of the c - bus latency time). if the CMX7031/cmx7041 has been set to decode a frame head before interrupting, it will check the crc portion of the frame head control field. if this indicates a corrupt frame head then a search for a new frame sync pattern will be automatically restarted. ffsk may be transmitted in conjunction with a ctcss or dcs sub - audio component. the device will handle the sub - audio signals as previously described. if a sub - audio signal turns off during reception of ff sk, it is up to the host c to turn off the decoding as the device will continue receiving and processing the incoming signal until commanded otherwise by the host c. the host c must keep track of the message length or otherwise determine the end of rece ption (e.g. by using sub - audio information to check for signal presence) and disable the demodulator at the appropriate time. note that when using packets with embedded size information, the CMX7031/cmx7041 will indicate when the last data block has been r eceived. 7.9.2 transmitting msk/ffsk signals the msk/ffsk encoding operates in accordance with the bit settings in the modem control register ($c7). when enabled the modulator will begin transmitting data using the settings and values in block 0 of the programm ing register (bit sync and frame sync patterns), the modem control register and the tx data registers. therefore, these registers should be programmed to the required values before transmission is enabled. the CMX7031/cmx7041 generates its own internal dat a clock and converts the binary data into the appropriately phased frequencies, as shown in figure 19 and table 11 . the binary data is taken from tx data 1 and 2 registers ($ca and $cb), mo st significant bit first. the following data words must be provided over the c - bus within certain time limits to ensure the selected baud rate is maintained. the time limits will be dependent on the data coding being used, see table 13 .
the two - way radio processor CMX7031/cmx7041 ? figure 19 modulating waveforms for 1200 and 2400 baud msk/ffsk signals the table below shows the combinations of frequencies and number of cycles to represent each bit of d ata, for both baud rates. table 11 data frequencies for each baud rate baud rate data frequency number of cycles 1200baud 1 1200hz one 0 1800hz one and a half 2400baud 1 1200hz half 0 2400hz one note: ffsk may be transmitt ed in conjunction with a ctcss or dcs sub - audio component. 7.10. msk / ffsk data packetising the CMX7031/cmx7041 has extensive data packetising features that can be controlled by the modem control register ($c7). the CMX7031/cmx7041 can packetise data in a variety of formats so the user can have the optimum data throughput for various signal to noise ratios. data is transferred in packets or frames, each frame is made up of a frame head followed by any associated user data. the frame head is composed of a 16 - bit bi t sync and 16 - bit frame sync pattern immediately followed by a 4 bytes control field. the 4 bytes start with an 8 - bit address followed by 1 byte carrying information about the format of the following data block. the next byte indicates the size of the pack et or can be used freely, depending on the format selected. the last byte is a checksum to detect if any of the 4 control field bytes has been corrupted. 7.10.1 tx hang bit when transmitting msk/ffsk data of formats 0, 2 or 3, the user should ensure that the data is terminated with a hang bit. to do this, the host must set the 'last data' bit in the modem control register ($c7) after the last data word has been loaded into the tx data 1 register ($ca), as described in section 9.1.25 i n the CMX7031/cmx7041 user manual . this will append a hang bit onto the end of the current word and will stop modulating after the hang bit has been transmitted. it will also generate an interrupt (if enabled) when the hang bit has left the modulator. 7.10.2 fr ame format ? --------------------------------- frame head --------------------------------- ? ? -------- data block -------- ? ? --- sync field --- ? ? ------------------ control field ------------------ ? bit sync frame sync address byte format byte size^ or user byte check - sum a data bytes check - sum b* 16 bits 16 bits byte 1 byte 2 byte 3 byte 4 * checksum b not applied to all data block types ^ byte 3 is only reserved on sized data blocks. r x s i g n a l i / p l o g i c ' 1 ' l o g i c ' 0 ' 2 4 0 0 b a u d l o g i c ' 1 ' l o g i c ' 0 ' r x s i g n a l i / p 1 2 0 0 b a u d l o g i c ' 1 ' l o g i c ' 0 ' l o g i c ' 1 ' l o g i c ' 0 '
the two - way radio processor CMX7031/cmx7041 ? the data block is made up from the user data. this consists of a variable number of data bytes optionally encoded to ensure secure delivery over a radio channel to the receiver. checksum b is only applied at the end of sized data blocks, the receiver can then detect if any of the user data has been corrupted. checksum b is composed of 16 bits for messages ? 16 bytes and 32 bits for longer messages. 7.10.3 frame head the frame head allows the receiver to detect and lock on to msk/ffsk signals, provides basic addressing to screen out unwanted messages and indicates the format, c oding and length of any following data. in frame formats 3, 4 and 5, the four control field bytes have forward error correction (fec) applied to them in the transmitter, this adds 4 bits to every byte and the receiver can correct errors in the received byt es. the 4 received bytes are then checked for a correct crc, so that corrupted frame heads can be rejected. if checksum a indicates that the control field bytes are correct, the address (byte 1) is compared with that stored in the msk header address bits o f modem address register, $b6 (b15:8). if a match occurs, or if the received address is '40', then an interrupt is raised indicating a valid frame head has been received. the frame head is 80 bits long (16 + 16 + {4x12}). the contents of a received frame h ead can be read from rx data registers $c5 and $c9. 7.10.4 data block coding the data block follows the frame head and can be coded with different levels of error correction and detection. the data block format is controlled by frame format selected in frame head byte 2, see also section 9.1.22 in the CMX7031/cmx7041 user manual . messages can take the following formats: format: description: 0 un - formatted data . this mode should be used with the en_raw bit (b10 of the modem control reg ister) set to 1. the interleave and scrambler settings are ignored. this mode can be useful when interfacing to a system using a different format to those available. in transmit, the device will transmit only the data loaded into the txdata 1 register. the host should provide bit sync, frame sync and any required formatting data as well as the data block through this register. in receive, the device will search for the programmed 16 - bit frame sync pattern, which is reported in the rx data 1 register as the first two received bytes, and then output all following data 16 bits at a time. the host will have to perform all other data formatting. 1 frame head only . no data block will be added. this format can be useful for indicating channel or user status by us ing byte 3 and the user bit of the frame head (see section 9.1.22 in the CMX7031/cmx7041 user manual ). 2 frame head followed by raw d ata . user data is appended to the frame head in 2 - byte units with no formatting or crc added by the CMX7031/cmx7041 . no size information is set in the frame head and data block may contain any even number of bytes per frame. 3 frame head followed by fec coded d ata only . each byte of the user data has 4 bits of fec coding added. no size information is set in the frame head and data block may contain any even number of bytes per frame. no crc is added to the data. 4 frame head followed by fec coded d ata with an automatic crc at the end of the data block. the number of user data bytes in the frame must be s et in frame head byte 3. the crc is automatically checked in the receiver and the result indicated to the host c. up to 255 bytes of user data can be sent in each frame using this format. 5 as 4 above, with the addition of all data block bytes being inter leaved . this spreads the transmitted information over time and helps reduce the effect of errors caused by fading. interleaving is performed on blocks of 4 bytes, the CMX7031/cmx7041 automatically adds and strips out pad bytes to ensure multiples of 4 byt es are sent over the radio channel.
the two - way radio processor CMX7031/cmx7041 ? notes: ? format 0, 1, 2 and 3 have no size information requirement and do not reserve frame head byte 3. this byte may be freely used by the host c to convey information. in format 4 and 5 this byte must be set to the n umber of user bytes in the message attached to that frame head ( ? 255) to allow the receiver to correctly decode and calculate the crc. ? format 0 data transfers do not provide any frame formatting. in tx the host c must transfer the bit and frame sync data before sending the message data. in rx the host c must decode all data after the frame sync. table 12 data block formatting types data block format: total over - air bits for an 80 - byte message air time for msk/ffsk message (ms) ov e r - air efficiency burst length protection at 1200baud [for 2400baud divide both times by 2] probability of detecting errors at at 1200baud 2400baud 2 720 600 300 89% none zero 3 1040 867 433 62% <0.83ms in any 10ms poor 4 1088 907 453 59% <0 .83ms in any 10ms excellent 5 1088 907 453 59% <3.33ms in any 40ms excellent higher levels of error protection have the penalty of adding extra bits to the over air signal and this reduces the effective bit rate. less error protection increases the effec tive bit rate, however in typical radio conditions the penalty is a greater risk of errors leading to repeated messages and a net reduction in effective bit rate compared to using error correction and detection. 7.10.5 crc and fec encoding information for message s with fec coding the following matrix is used to calculate and decode bytes: data bits fec bits 7 6 5 4 3 2 1 0 3 2 1 0 1 1 1 0 1 1 0 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 0 1 0 1 0 0 0 1 8 bit crc is used in all frame h eads with the following generator polynomial (gp): x 8 + x 7 + x 4 + x 3 + x 1 + x 0 16 bit crc is used at the end of sized data messages of up to 16 bytes with the following gp: x 16 + x 12 + x 5 + x 0 32 bit crc is used at the end of sized data messages of o ver 16 bytes with the following gp: x 32 + x 31 + x 30 + x 28 + x 27 + x 25 + x 24 + x 22 + x 21 + x 20 + x 16 + x 10 + x 9 + x 6 + x 0 7.10.6 data interleaving the built in msk/ffsk packetising includes the option of interleaving t he data in each block (type 5). this, toget her with forward error correction (fec), reduces the effects of burst errors. interleaving does not add any bits to the message, the packet is assembled in 'rows' and then transmitting in 'columns'. data (8 bits) fec (4 bits) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 in the above example the packet is assembled as 4 rows with 12 bits of information per row. when this packet is interleaved the bits are sent over the communication channel in the following order: 0, 12, 24, 36, 1, 13, 25, 37, 2, 14, ... , 33, 45, 10, 22, 34, 46, 11, 23, 35, 47.
the two - way radio processor CMX7031/cmx7041 ? in the receiving modem the packet is re - assembled (de - interleaved) before error correction. the CMX7031/cmx7041 has a built in packet receive modem which is able to recognise (by using the frame head bytes) when the data has been interleaved by the transmitter and will decode the data using the correct method. 7.10.7 data scrambling/privacy coding it is preferable for msk/ffsk over - a ir data to be reasonably random in nature to ensure the receiver can track timing using the bit changes and to smooth the frequency spectrum. to reduce the possibility of user data causing long strings of 1s or 0s to be transmitted, a 16 - bit data scrambl er is provided and operates on all bits after the frame head. the default (standard) setting for this scrambler is with a start code (seed) of $ffff and any receivers with the same seed may decode this data. however, if the transmitter and receiver pre - arr ange a different seed then the scrambler will start its sequence in another place and any simple receiver that does not know the transmitted seed will not be able to successfully decode the data. this method gives over 65,000 different starting points and the chance of others decoding data successfully is reduced. the CMX7031/cmx7041 provides the option of two custom 16 - bit words that are programmable by the user in programming register p0.4 to p0.7. bits 0 and 1 in the frame head format byte indicate which setting (standard, seed1, seed2 or none) the following data block has been scrambled with, see section 9.2.1 in the CMX7031/cmx7041 user manual . note that a seed of $0000 will effectively turn off the scrambler and provide no protection against long sequences of 1s or 0s. reception of scrambled data will only be successful when the receiving device has been programmed with the correct (identical) seed to that used by the transmitter. by using this method the CMX7031/cmx7041 provides a privacy code that will protect against casual monitoring, however the data is not encrypted and a sophisticated receiver can decode the data by using moderately simple decoding techniques. if data encryption is required it must be performed by t he host c. the scrambler function is controlled by bits 0, 1 of the modem control register, $c7. 7.10.8 data buffer timing data must be transferred at the rate appropriate to the signal type and data format. the CMX7031/cmx7041 buffers data in two 16 - bit registe rs. the CMX7031/cmx7041 will issue interrupts to indicate when data is available or required. the host must respond to these interrupts within the maximum allowable latency for the signal type. table 13 shows the maximum latencies for transferring signal data to maintain appropriate data throughput. table 13 maximum data transfer latency data format max. time to read from or write to data buffer data buffer size 1200 baud 2400 baud 0 13.3ms 6.6ms 2 byte s 1 n/a* n/a* 4 bytes 2 13.3ms 6.6ms 2 bytes 3 20ms 10ms 2 bytes 4 40ms 20ms 4 bytes 5 40ms 20ms 4 bytes * type 1 message is an isolated frame head, there is no subsequent data to load (tx) or read (rx).
the two - way radio processor CMX7031/cmx7041 ? 7.11. fsk 1200bps dsc m odem in place of the msk/ff sk modem described in section 7.9 , the device can implement a 1200 bps dsc (digital selective call) modem conforming to the requirements of itu - r m.493 - 11 for use in marine vhf band radio equipment. selecting th is function will disable the msk/ffsk modems. this modem uses tones at 1300 and 2100hz to represent binary 1s and 0s respectively, with 6db/octave pre - emphasis in tx. dot pattern dx/rx a b c d e f g h i phasing sequence format specifier called party ad dress category self - identification tele - command message frequency message frequency message end of sequence error - check character 2 identical characters 5 characters 1 character 5 characters 2 characters 3 characters 3 characters 3 identical dx charac ters 1 rx character 1 character dot p attern d x d x d x d x d x d x a a b l b 2 b 3 r 4 b 5 c d l d 2 d 3 d 4 d 5 e l e 2 f l f 2 f 3 g l g 2 g 3 h i h h r x 7 r x 6 r x 5 r x 4 r x 3 r x 2 r x 1 r x 0 a a b l b 2 b 3 b 4 b 5 c d 1 d 2 d 3 d 4 d 5 e l e 2 f l f 2 f 3 g l g 2 g 3 h i figure 20 dsc f ormat to enable this mode, the en_dsc (bit 11 of the modem control register, $c7) must be set. this will disable the msk/ffsk modem features. the dsc modem itself can t hen be controlled by setting or clearing en_1200 (bit 2 of the mode control register, $c1). note that, due to the c - bus latency times, there should be a delay after clearing this bit, before re - enabling it again (see 7.2.1 ). w ith dsc mode selected, bits 8 to 0 of the modem control register, $c7, are ignored. two modes of operation are provided: o raw mode o formatted mode (normal or enhanced ) enhanced operation is available by setting program register p0.0 bit 10 and provides: o supp ort for dsc expansion sequences (itu - r m.821 - 1) o support for transmission of continuous distress signals.
the two - way radio processor CMX7031/cmx7041 ? symbol emitted signal symbol emitted signal symbol emitted signal no. and bit position no. and bit position no. and bit position 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 00 bbbbbbbyyy 43 yybybybbyy 86 byybybybyy 01 ybbbbbbyyb 44 bbyybybybb 87 yyybybybyb 02 bybbbbbyyb 45 ybyybybbyy 88 bbbyybyybb 03 yybbbbbyby 46 byyybybbyy 89 ybbyybybyy 04 bbybbbbyyb 47 yyyybybbyb 90 byby ybybyy 05 ybybbbbyby 48 bbbbyybyby 91 yybyybybyb 06 byybbbbyby 49 ybbbyybybb 92 bbyyybybyy 07 yyybbbbybb 50 bybbyybybb 93 ybyyybybyb 08 bbbybbbyyb 51 yybbyybbyy 94 byyyybybyb 09 ybbybbbyby 52 bbybyybybb 95 yyyyybybby 10 bybybbbyby 53 ybybyybbyy 96 bb bbbyyyby 11 yybybbbybb 54 byybyybbyy 97 ybbbbyyybb 12 bbyybbbyby 55 yyybyybbyb 98 bybbbyyybb 13 ybyybbbybb 56 bbbyyybybb 99 yybbbyybyy 14 byyybbbybb 57 ybbyyybbyy 100 bbybbyyybb 15 yyyybbbbyy 58 bybyyybbyy 101 ybybbyybyy 16 bbbbybbyyb 59 yybyyybbyb 1 02 byybbyybyy 17 ybbbybbyby 60 bbyyyybbyy 103 yyybbyybyb 18 bybbybbyby 61 ybyyyybbyb 104 bbbybyyybb 19 yybbybbybb 62 byyyyybbyb 105 ybbybyybyy 20 bbybybbyby 63 yyyyyybbby 106 bybybyybyy 21 ybybybbybb 64 bbbbbbyyyb 107 yybybyybyb 22 byybybbybb 65 ybbb bbyyby 108 bbyybyybyy 23 yyybybbbyy 66 bybbbbyyby 109 ybyybyybyb 24 bbbyybbyby 67 yybbbbyybb 110 byyybyybyb 25 ybbyybbybb 68 bbybbbyyby 111 yyyybyybby 26 bybyybbybb 69 ybybbbyybb 112 bbbbyyyybb 27 yybyybbbyy 70 byybbbyybb 113 ybbbyyybyy 28 bbyyybbybb 71 yyybbbybyy 114 bybbyyybyy 29 ybyyybbbyy 72 bbbybbyyby 115 yybbyyybyb 30 byyyybbbyy 73 ybbybbyybb 116 bbybyyybyy 31 yyyyybbbyb 74 bybybbyybb 117 ybybyyybyb 32 bbbbbybyyb 75 yybybbybyy 118 byybyyybyb 33 ybbbbybyby 76 bbyybbyybb 119 yyybyyybby 34 by bbbybyby 77 ybyybbybyy 120 bbbyyyybyy 35 yybbbybybb 78 byyybbybyy 121 ybbyyyybyb 36 bbybbybyby 79 yyyybbybyb 122 bybyyyybyb 37 ybybbybybb 80 bbbbybyyby 123 yybyyyybby 38 byybbybybb 81 ybbbybyybb 124 bbyyyyybyb 39 yyybbybbyy 82 bybbybyybb 125 ybyyyyybb y 40 bbbybybyby 83 yybbybybyy 126 byyyyyybby 41 ybbybybybb 84 bbybybyybb 127 yyyyyyybbb 42 bybybybybb 85 ybybybybyy b = 0 order of transmitted bits: bit 1 first y = 1 figure 21 dsc character f ormat 7.11.1 receiving 1200 bps fsk (dsc) signals in rx raw mode (en_raw=1) the modem will report back all data received as soon as it is enabled. (note: if a valid dsc signal is not present when the modem is first enabled, it will still attempt to demodulate the input signal and output data . the host must determine if the data is valid or not. it is possible to use the sync facility to reduce the amount of invalid data presented to the host, but this may also lead to dsc calls with errors in the sync pattern being missed).
the two - way radio processor CMX7031/cmx7041 ? as soon as the en_ 1200 bit has been asserted, the modem will attempt to demodulate the input signal. data bits will then be delivered to the rx data 1 register, $c5 as they are demodulated, indicated by the data_rdy bit. it is up to the host to align, decode and validate th e data and to subsequently switch the modem off once an eos (end of sequence) has been detected (by clearing bit 2 of the mode control register, $c1). in this mode, the device does not perform byte alignment or phasing (synchronisation) detection 4 . the hos t must read the rxdata 1 register before the next 16 bits of data have been received, otherwise the data will be lost. if the sync facility is used in raw mode, then the value of sync must be programmed by the host to a suitable value via the program regis ters (p0.0 and p0.1). the values $5555 or $aaaa are suggested for this setting, however, this will not completely remove false detections and the following received data must be analysed before assuming that a valid call is in progress (see itu - r m.493 - 11 for details). the sync enable bit (bit 15 of the modem control register, $c7) must be asserted. setting the en_1200 bit (bit 2 of the mode control register, $c1), will activate the dsc modem which will then attempt to decode the signal at its input. acqui sition of the sync data pattern will be reported to the host by the setting of the 1k2 bit (bit 3 in the status register, $c6). in rx formatted mode, (en_raw=0) the modem will check the incoming bit stream for a valid sequence of phasing characters (3x rx, 2x dx+ rx or dx + 2 x rx) and then report any correctly decoded characters in the rxdata1 ($c5) register. the characters are packed into the 16 - bit register as two 7 bit characters and an additional error indication bit (bits 15 and 7). in the case where an odd number of characters has been received, the unused field will be reported as 0000000 b and the error bit set to 1. this mechanism significantly reduces the amount of data transferred to the host and the host processing requirements. the decoded 7 - bit characters will be delivered to the rxdata1 register, $c5, as indicated by the data_rdy bit. the modem will not report valid data until it has correctly received the initial phasing sequence. once the phasing sequence has been detected, the modems intern al dpll bandwidth will be automatically reduced to improve the error performance. if one of the time - diversity received characters is in error, only the correct one will be reported. if both characters have errors, the last one received will be reported, w ith bit 7 (msb) set. the characters reported back will correspond to the data sequence (see figure 20 ) 5 : a a b1 b2 b3 b4 b5 c d1 d2 d3 d4 d5 e1 e2 f1 f2 f3 g1 g2 g3 h i if enhanced dsc support is enabled the modem will look for f urther da ta following the end of the main sequence. if a n expansion sequence (as defined by itu - r m.821 - 1) is detected , the contents will continue to be delivered to rxdata1 until the end of th e expansion sequence . if either the main sequence or expansion sequences contained an odd number of bytes the unused field will be reported as 0000000 b and the error bit set to 1 . this means that an expansion sequence will always start on a register boundary. when the end of the received message is detected the d ata_e nd bit will be set in the s tatus register ( $c6 ). main message g 2 g 3 h i h h a e 1 b e 1 b e 2 b e 3 b e 4 a e 2 c e 1 c e 2 c e 3 c e 4 d e e e d e d e f 2 f 3 g 1 g 2 g 3 h i x x a e 1 b e 1 b e 2 b e 3 b e 4 a e 2 c e 1 c e 2 c e 3 c e 4 d e e e figure 22 expanded dsc f ormat 4 this is similar to the cmx604, cmx910 and cmx7032 operation. 5 this particular sequence corresponds to the example giv en in itu - r m.493 - 11. different telecommands will produce different sequences of varying lengths.
the two - way radio processor CMX7031/cmx7041 ? ae1 first expansion data specifier (100 to 106) ae2 second expansion data specifier (100 to 106) bex characters of first expansion message cex characters of second expansion message de eos end of sequence ee ecc error check character x no information (126) f2 f3 g1 g2 g3 h i ae 1 be1 be2 be3 be4 ae2 ce1 ce2 ce3 ce4 de ee note that if a normal dsc sequence is received with enhanced dsc enabled, there will be a delay in setting the data_end bit whi lst th e modem processes the remainder of the signal for a possible expansion sequence, indicated by one of the expansion characters (100 to 10 6) in the correct position . 7.11.2 transmitting 1200 bps fsk (dsc) signals in tx raw mode (en_raw=1) the host must supply all d ata to be transmitted by the modem via the txdata register ($ca) in the correct order and format to conform to the dsc standards. setting the en_1200 bit (bit 2 of the mode control register, $c1), will enable the dsc modem which will then transmit the data supplied by the host through the txdata1 register, $ca. bit 10 of the modem control register, $c7, should also be set to enable / disable raw data mode as appropriate. in tx formatted mode (en_raw=0), the modem will automatically transmit the dotting patter n followed by the phasing sequence and then encode the data presented at the txdata1 register ($ca) with the correct checksum bits and then transmit it in the correct position with automatic repetition to conform to the time diversity requirements of the s tandard. data in the txdata1 r egister is presented as two 7 - bit characters, in the case where an odd number of characters needs to be sent, then the un - used character should be set to 0000000 and b7 set to 1. the final characters sent by the host should be a valid end - of - sequence character followed by the error check character. valid dsc characters should be supplied by the host through the txdata1 register, $ca. two characters can be loaded in the same c - bus write operation. the modem will begin transm itting the dotting sequence followed by the phasing sequence as soon as the en_1200 bit (bit 2 of the mode control register, $c1) is set. the format of the data supplied by the host is similar to the rx format: a a b1 b2 b3 b4 b5 c d1 d2 d3 d4 d5 e1 e2 f1 f2 f3 g1 g2 g3 h i there is no facility for automatically generating continuous dotting (preamble), y data (all 1s), b data (all 0s) or phasing (synchronisation) sequences internally, however, the modem will continue to transmit the last data loaded int o the txdata1 register, so only a single data load is required. if a dsc expansion sequence (as defined by itu - r m.821 - 1) is required to be transmitted (and the enhanced dsc support is enabled) it should follow on directly from the main sequence end. if th e main sequence had an odd number of bytes the padding byte (000 0000 b with error bit set) should still be included following the error check character (i). the expansion sequence should be transmitted in the same format as the original message, using the t xdata1 register. the last characters should be the eos and ecc characters of the expansion sequence, ( plus a padding byte , 000 0000 b , with error bit set if the expansion sequence contained an odd number of bytes ) . on writing the last data , the data_end bit should be set in the modem control register ( $c7 ). the maximum number of over - air characters in an expansion sequence is 38 (corresponds to 17 formatted characters , including eos and ecc ) . the enhanced dsc support feature also allows a special case for dis tress messages. if a distress message is transmitted following a previous sequence end , the transmission will continue automatically. this will cause the modem to generate another dotting and phasing sequence without a break in transmission. this allows ge neration of a distress signal with multiple continuous repetitions as described in itu - r m . 493 , section 11.1 . the modem does not buffer the message bytes after they have been transmitted so the host must send the same sequence multiple times in order to im plement the sequence repetition. the special case of a distress signal is detected by the next sequence start ( characters a1 and a2) both having the value 112 following the end of the previous sequence. (this is the value which denotes a distress message .)
the two - way radio processor CMX7031/cmx7041 ? 7.12. psk encoder a 559bps psk modem is provided to enable transmission of signalling suitable for suitable radio systems. this uses the same tx data interface as the dsc modem in raw mode and is enabled by setting b4 of the modem control register, $c7 along with b10 and b11. this will output 2 ? cycles of the audio carrier tone (1398hz) for each data bit. the phase inversion occurs at the zero - crossing point. modem control ($c7) = $0c10 txdata 1 ($ca) = user tx data mode control ($c1) = $0006 7.13. noaa / nwr sa me and wat d ecoding a data decoder and tone detector suitable for use with the noaas nwr (noaa weather radio) system is provided in the device. full details of the system are publicly available from the noaa web site at http://www.nws.noaa.gov/nwr/ and the CMX7031/cmx7041 provides support for the wat detection and same decoding. it is possible to route the signal input to either input 1 or input 2 so that nwr monitoring can be performed in parallel with existin g radio operations (subject to suitable rf sections being provided externally). see: o nwr status and data C $bb read o mode control C $c1 write o status C $c6 read o modem control C $c7 write o interrupt mask C $ce write the nwr same data message consists of six possible elements in the following sequence: 1 preamble 2 header code 3 warning alarm tone/attention signal 4 voice message 5 preamble 6 en d of message (eom) elements 1, 2, 5, and 6 will always be transmitted in a nwr same message and repeated three times. elements 3 and 4 may or may not be transmitted depending on the specific type of message or its application. the coded message is transmi tted, using frequency shift keying (fsk), in the nwr audio channel. in this application and the implementation currently used by the fcc eas, it is more accurate to refer to the code format as audio frequency shift keying (afsk). it is transmitted at no le ss than 80% modulation ( 4.0 khz deviation minimum, 5.0 khz deviation maximum). the coded message and voice message is transmitted over the nwr transmitter network using standard pre - emphasis for narrow band vhf frequency modulation (fm) of 6 db per oct ave increasing slope from 300 hz to 3,000 hz applied to the modulator. preamble. the preamble and header code are transmitted three times with a one second pause ( 5%) between each coded message burst prior to the broadcast of the actual voice message. th en the preamble and end of message (eom) code are transmitted three times with a one second pause ( 5%) between each eom burst. preamble byte. the first 16 bytes (prior to the header code and eom) of the data transmission constitute a preamble with each b yte having the value $ab (8 bit byte [10101011]). for all bytes, the least significant bit (lsb) is sent first. the bytes following the preamble constitute the actual message data transmission. note: for nwr system maintenance, nws will occasionally send a continuous string of preamble code, $ab or a continuous tone through its communications links to the nwr transmitters, for several seconds up to around one minute.
the two - way radio processor CMX7031/cmx7041 ? bit definition. the following definitions of a bit are based on a bit period equaling 1920 microseconds ( one microsecond). o the data rate is 520.83 bits per second o logic zero is 1562.5 hz. o logic one is 2083.3 hz o mark and space bit periods are equal at 1.92 milliseconds. header. bit and byte synchronization is attained by the preamble code at t he beginning of each header code or eom data transmission. the message data (header) code is transmitted using american standard code for information interchange (ascii) characters as defined in ansi incits 4 (rev 86, 2002), with the eighth bit always set to zero. each separate header code data transmission should not exceed a total of 268 bytes if the maximum allowable geographic locations (31) are included. warning alarm tone. the warning alarm tone (wat), if transmitted, is sent within one to three secon ds following the third header code burst. the frequency of the wat is 1050hz ( 0.3%) for 8 to 10 seconds at no less than 80% modulation ( 4.0 khz deviation minimum, 5.0 khz deviation maximum). voice message . if transmitted, the actual voiced message be gins within three to five seconds following the last nwr same code burst or wat, whichever is last. the voice audio ranges between 20% modulation ( 1 khz deviation) and 90% modulation ( 4.5 khz deviation) with occasional lulls near zero and peaks as high as, but not exceeding, 100% modulation ( 5.0 khz deviation). total length of the voice message should not exceed two minutes. preamble . a repeat of preamble above. end of message . eom is identified by the use of nnnn. 7.13.1 message code format (preamble)zczc - org - eee - pssccc - pssccc+tttt - jjjhhmm - llllllll - (1 second pause) (preamble)zczc - org - eee - pssccc - pssccc+tttt - jjjhhmm - llllllll - (1 second pause) (preamble)zczc - org - eee - pssccc - pssccc+tttt - jjjhhmm - llllllll - (1 to 3 second pause) 1050 hz warning alarm tone for 8 t o 10 seconds C (if transmitted) (3 to 5 second pause) voice /spoken oral text of message C (if transmitted) (1 to 3 second pause) (preamble) nnnn (1 second pause) (preamble) nnnn (1 second pause) (preamble) nnnn 7.13.2 wat d etection the wat detector is enabled by setting the nwr bit (b12 of $c1) and indicated by setting b15 of the nwrdata register ($bb). if enabled, the nwr irq (b14) in the status register ($c6) will also be set. the detector will be reset after 500ms, so multiple detections may be indicated on lo ng wat tones. 7.13.3 same d ecoding the same data is received at 520.83bps and decoded by the CMX7031/cmx7041 whenever the nwr bit (b12 of $c1) is set. internally, the CMX7031/cmx7041 monitors the selected input until it detects the preamble sequence and then pass es the subsequently recovered data to the host uc via the nwrdata register ($bb). the decoder will detect the data header and determine if it is zczc indicating that data follows or nnnn indicating the end of a transmission and report these states in b its 13 and 14 of the nwrdata register ($bb) respectively). if enabled, the nwr irq (b14) in the status register ($c6) will also be set following the detection of the preamble and on every subsequently received byte.
the two - way radio processor CMX7031/cmx7041 ? when the en_nwr_data bit is set, the rec eiver outputs the received bitstream. the host is allowed to set this bit at any time to get "raw mode" data output with no preamble/header detection and no guarantee of byte alignment. when the en_nwr_data bit is clear, the receiver searches for a valid s ame transmission but does not output data. if it sees a preamble followed by the data header ("zczc"), it raises an irq and *automatically* sets the en_nwr_data bit to put itself into data - output mode. it is then up to the host to decide when to clear th e en_nwr_data bit to put the receiver back into sync - search mode (thus "re - arming" it). if the receiver sees a preamble followed by the end - of - message header ("nnnn") while doing sync - search, it informs the host [2] and then continues the search without pu tting itself into data - output mode. it is the responsibility of the host to shut the decoder down at the end of a received burst by clearing the en_nwr_data bit (b12 of $c7) to 0. 7.14. auxiliary adc operation the inputs to the two auxiliary adcs can be indepen dently routed to any of the signal input pins under control of the auxadc and tx mod mode register, $a7. conversions will be performed as long as a valid input source is selected, to stop the adcs, the input source should be set to none. register $c0, b6 , bias, must be enabled for auxiliary adc operation. averaging can be applied to the adc readings by selecting the relevant bits in the auxadc and tx mod mode register, $a7, the length of the averaging is determined by the value in the programming register (p3.0 and p3.1), and defaults to a value of 0. this is a rolling average system such that a proportion of the current data will be added to the last value. the proportion is determined by the value of the average counter in p3.0 and p3.1. for an average v alue of 0; 50% of the current value will be applied, for a value of 1 = 25%, 2 = 12.5% etc. the maximum useful value of this field is 8. high and low thresholds may be independently applied to both adc channels (the comparison is applied after averaging, i f this is enabled) and an irq generated if a rising edge passes the high threshold or a falling edge passes the low threshold, see figure 23 . the thresholds are programmed via the auxadc threshold register, $b5. auxiliary adc data is read back in the auxadc data registers ($a9 and $aa) and includes the threshold status as well as the actual conversion data (subject to averaging, if enabled). figure 23 auxadc irq o peration signal irq irq irq irq high threshold low threshold
the two - way radio processor CMX7031/cmx7041 ? se e: o auxadc and tx mod mode C $a7 write o auxadc1 data C $a9 read o auxadc2 data C $aa read o auxadc threshold data C $b5 write 7.15. auxiliary dac / r amdac operation the four auxiliary dac channels are programmed via the auxdac control register, $a8. auxdac channel 1 may also be programmed to operate as a ramdac which will automatically output a pre - programmed profile at a programmed rate. the auxdac co ntrol register, $a8, with b12 set, controls this mode of operation. the default profile is a raised cosine (see table 18 ), but this may be over - written with a user defined profile by writing to programming register p3.11. the ramd ac operation is only available in tx mode and, to avoid glitches in the ramp profile, it is important not to change to idle or rx mode whilst the ramdac is still ramping. the auxdac outputs hold the user - programmed level during a powersave operation if lef t enabled, otherwise they will become tri - state (high impedance). note that access to all four auxdacs is controlled by the auxdac control register, $a8, and therefore to update all auxdacs requires four writes to this register. it is not possible to simul taneously update all four auxdacs. see: o auxdac control / data C $a8 write 7.16. rf synthesiser (CMX7031 only) the CMX7031 includes two integer - n rf synthesisers, each comprising a divider, phase comparator and charge pump. the divider ha s two sets of n and r registers: one set can be used for transmit and the other for receive. the division ratios can be set up in advance by means of c - bus registers. a single c - bus command will change over from the transmit to the receive division ratios , or vice versa, enabling a fast turnaround. see: o rf channel data C $b2 write o rf channel control C $b3 write o rf cha nnel status C $b4 8 - bit read e xternal rf components are needed to complete the synthesiser circuit. a typical schematic for one synthesiser, with external components, is shown in figure 24 . figure 24 example rf synthesiser component s for a 512mhz receiver
the two - way radio processor CMX7031/cmx7041 ? r31 0 ? c31 820pf r32 18k ? c32 8.2nf r33 18k ? c33 680pf c34 1nf c35 1nf resistors ? 5%, capacitors and inductors ? 20% unless otherwise stated. note: r31 is chosen within the range 0 ? to 30k ? and selects the nomin al charge pump current. it is recommended that c34 and c35 are kept close to the vco and that the stub from the vco to the CMX7031/cmx7041 is kept as short as possible. the loop filter components should be placed close to the vco. figure 25 single rf channel block diagram the two rf synthesisers are programmable to any frequency in the range 100mhz to 600mhz. figure 25 is a block diagram of one synthesiser channel. the rf synthesiser cloc k is selectable between the xtal or the clock supplied to the rfclk input pin. the rf synthesiser clock is common to both channels. the charge pump supply (cpvdd) is also common to both channels. the rf input pins, cpout, iset and rfv ss pins are channel sp ecific and designated as either rf1p, rf1n, cp1out, iset1, rfv ss or rf2p, rf2n, cp2out, iset2, rfv ss on the signal list in section 3 . the n and r values for tx and rx modes are channel specific and can be set from the host c v ia the c - bus. various channel specific status signals are also accessible via c - bus. the divide by n counter is 20 bits; the r counter is 13 bits. typical external components are shown in figure 24 . both synthesiser s are phase locked loops (plls) of the same design, utilising external vcos and loop filters. the vcos need to have good phase noise performance although it is likely that the high division ratios used will result in the dominant noise source being the ref erence oscillator. the phase detectors are of the phase - frequency type with a high impedance charge pump output requiring just passive components in the loop filter. lock detect functions are built in to each synthesiser and the status reported via c - bus. a transition to out - of - lock can be detected and communicated via a c - bus interrupt to the host c. this can be important in ensuring that the transmitter cannot transmit in the event of a fault condition arising. two levels of charge pump gain are availabl e to the user, to facilitate the possibility of locking at different rates under program control. a current setting resistor (r31) is connected between the iset pin (one for each pll system) and the respective rfv ss . this resistor will have an internally g enerated band gap voltage expressed across it and may have a value of 0 ? to 30k ? , which (in conjunction with the on - chip series resistor of 9.6k ? ) will give charge pump current settings over a range of 2.5ma down to 230a
the two - way radio processor CMX7031/cmx7041 ? (including the control bit variati on of 4 to 1). the value of the current setting resistor (r31) is determined in accordance with the following formulae: gain bit set to 1: r31 (in ) = (24/icp) C 9600 gain bit cleared to 0: r31 (in ) = (6/icp) C 9600 where icp is the charge pump current (in ma). note that the charge pump current should always be set to at least 230a. the gain bit refers to either bit 3 or bit 11 in the rf channel control register, $b3. the step size (comparison frequency) is programmable; to minimise the effects of phase noise this should be kept as high as possible. this can be set as low as 2.5khz (for a reference input of 20mhz or less), or up to 200khz C limited only by the performance of the phase comparator. the frequency for each synthesiser is set by using two registers: an r register that sets the division value of the input reference frequency to the comparison frequenc y (step size), and an n register that sets the division of the required synthesised frequency from the external vco to the comparison frequency. this yields the required synthesised frequency (fs), such that: fs = (n / r) x f ref where f ref is the sele cted reference frequency other parameters for the synthesisers are the charge pump setting (high or low) since the set - up for the plls takes 4 x rf channel data register writes it follows that, while updating the pll settings, the registers may contain unwanted or intermediate values of bits. these will persist until the last register is written. it is intended that users should change the content of the rf channel data register on a pll that is disabled, powersaved or selected to work from the altern ate register set (tx and rx are alternate register sets). there are no interlocks to enforce this intention. the names tx and rx are arbitrary and may be assigned to other functions as required. they are independent sets of registers, one of which is selected to command each pll by changing the settings in the rf channel control C $b3 write register. for optimum performance, a common master clock should be used for the rf synthesisers (rf clock) and the bas eband sections (main and auxiliary system clocks). using unsynchronised clocks can result in spurious products being generated in the synthesiser output and in some cases difficulty may be experienced with obtaining lock in the rf synthesisers. lock statu s the lock status can be observed by reading the rf channel status register, $b4, and the individual lock status bits can (subject to masking) provide a c - bus interrupt. the lock detector can use a tolerance of one cycle or four cycles of the reference clo ck (not the divided version that is used as a comparison frequency) in order to judge phase lock. an internal shift register holds the last three lock status measurements and the lock status bits are flagged according to a majority vote of these previous t hree states. hence, one occasional lock error will not flag a lock fail. at least two successive phase lock events are required for the lock status to be true. note that the lock status bits confirm phase lock to the measured tolerance and not frequency l ock. the s ynthesiser may take more time to confirm phase lock with the lock status bits than the time to switch from channel to channel. the purpose of a 4 - cycle tolerance is for the case where a high frequency reference oscillator would not forgive a smal l phase error. rf inputs the rf inputs are differential and self biased (when not powersaved). they are intended to be capacitatively coupled to the rf signal. the signal should be in the range 0dbm to C 20dbm (not necessarily balanced). to ensure an accura te input signal the rf should be terminated with 50 as close to the chip as possible and with the p and n inputs capacitatively coupled to the input and ground, keeping these connections as short as possible. the rf input impedance is almost purely ca pacitative and is dominated by package and printed circuit board parasitics.
the two - way radio processor CMX7031/cmx7041 ? guidelines for using the rf synthesisers ? rf input slew rate (dv/dt) should be 14 v/s minimum. ? the rf synthesiser 2.5v digital supply can be powered from the vdec output pin. ? rf clock sources and other, different clock sources must not share common ic components, as this may introduce coupling into the rf. unused ac - coupled clock buffer circuits should be tied off to a dc supply , to prevent them oscillating. ? it is recommended tha t the rf synthesisers are operated with maximum gain iset (ie. iset tied to rfvss). ? the loop filter components should be optimised for each vco.
the two - way radio processor CMX7031/cmx7041 ? 7.17. digital system clock generators figure 26 digital cl ock generation schemes the CMX7031/cmx7041 includes a 2 - pin crystal oscillator circuit. this can either be configured as an oscillator, as shown in section 5 , or the xtal input can be driven by an externally generated clock. t he crystal (xtal) source frequency can go up to 12.288mhz (clock source frequency up to 24.576mhz), but a 6.144mhz xtal is assumed for the functionality provided in the CMX7031/cmx7041 . ref clk div / 1 to 512 $ ac b 0 - 8 pd vco pll div / 1 to 1024 $ ab b 0 - 9 lpf sysclk 1 ref sysclk 1 div vco op div / 1 to 64 $ ab b 10 - 15 sysclk 1 pre - clk $ ac b 11 - 15 sysclk 1 output 384 khz - 20 mhz 48 - 192 khz ( 96 khz typ ) sysclk 1 vco 24 . 576 - 98 . 304 mhz ( 49 . 152 mhz typ ) ref clk div / 1 to 512 $ ae b 0 - 8 pd vco pll div / 1 to 1024 $ ad b 0 - 9 lpf sysclk 2 ref sysclk 2 div vco op div / 1 to 64 $ ad b 10 - 15 sysclk 2 pre - clk $ ae b 11 - 15 sysclk 2 output 384 khz - 20 mhz 48 - 192 khz ( 96 khz typ ) sysclk 2 vco 24 . 576 - 98 . 304 mhz ( 49 . 152 mhz typ ) ref clk div / 1 to 512 p 3 . 4 pd vco pll div / 1 to 1024 p 3 . 5 lpf mainclk ref mainclk div vco op div / 1 to 64 p 3 . 3 b 12 - 7 p 3 . 6 b 12 - 7 mainclk pre - clk mainclk output 384 khz - 50 mhz ( 24 . 576 mhz typ ) 48 - 192 khz ( 96 khz typ ) mainclk vco 24 . 576 - 98 . 304 mhz ( 49 . 152 mhz typ ) to internal adc / dac dividers auxadc div p 3 . 3 b 6 - 0 p 3 . 6 b 6 - 0 aux _ adc ( 83 . 3 khz typ ) osc 3 . 0 - 12 . 288 mhz xtal or 3 . 0 - 24 . 576 mhz clock to rf synthesiser ref clk selection
the two - way radio processor CMX7031/cmx7041 ? 7.17.1 main clock operation a pll is used to create the main clock (nominall y 24.576mhz) for the internal sections of the CMX7031/cmx7041 . at the same time, other internal clocks are generated by division of either the xtal reference clock or the main clock. these internal clocks are used for determining the sample rates and conve rsion times of a - to - d and d - to - a converters, running a general purpose timer, the signal processing block and the rf synthesisers. in particular, it should be noted that in idle mode the setting of the gp timer divider directly affects the c - bus latency (w ith the default values this is nominally 250 s). the CMX7031/cmx7041 defaults to the settings appropriate for a 6.144mhz xtal, however if other frequencies are to be used (to facilitate commonality of xtals between the rf synthesisers and the CMX7031/cmx7041 for instance) then the program block regi sters p3.2 to p3.6 will need to be programmed appropriately at power - on. a table of common values is provided in table 2 . see: o program block 3 C auxdac, ramdac and clock c ontrol: 7.17.2 system clock operation tw o system clock outputs, sysclk1 and sysclk2, are available to drive additional circuits, as required. these are phase locked loop (pll) clocks that can be programmed via the system clock registers with suitable values chosen by the user. the system clock p ll configure registers ($ab and $ad) control the values of the vco output divider and main divide registers, while the system clock ref. configure registers ($ac and $ae) control the values of the reference divider and signal routing configurations. the pl ls are designed for a reference frequency of 96khz. if not required, these clocks can be independently powersaved. the clock generation scheme is shown in the block diagram of figure 26 . note that at power - on, these pins provide, b y default: CMX7031: xtal clk cmx7041: no signal (off) see: o sysclk 1 and 2 pll data C $ab, $ad write o sysclk1 and 2 ref C $ac and $ae write 7.18. gpio two pins on the CMX7031 or four pins on the cmx7041 are provided for gpio purposes. gpio 1 and 2 are driven by the CMX7031/cmx7041 to follow the state of the rx and tx mode bits in the mode register, $c1: $c1 mode b1 b0 txena rxena idle 0 0 1 1 rx 0 1 1 0 tx 1 0 0 1 reserved 1 1 1 1 with fi - 1. 3.8.2 onwards and on the cmx7041 only, gpio a and b are available as outputs controlled by the host using the gpio write function of the audiotone register, $cd. this function is provided to maintain compatibility for applications which can dual boot the c mx7141 fi - 1 functionality. at power - on their default state is high impedance. 7.19. signal level optimisation the internal signal processing of the CMX7031/cmx7041 will operate with wide dynamic range and low distortion only if the signal level at all stages in the signal processing chain is kept within the recommended limits. for a device working from a 3.3v 10% supply, the maximum signal level which can be accommodated without distortion is [(3.3 x 90%) C (2 x 0.3v)] volts pk - pk = 838mv rms, assuming a sine wa ve signal. compared to the reference level of 308mv rms , this is a signal of +8.69db. this should not be exceeded at any stage. the various level adjustment facilities are shown in figure 27 .
the two - way radio processor CMX7031/cmx7041 ? figure 27 level adjustments 7.19.1 transmit path levels for the maximum signal out of the mod1 and mod2 attenuators, the signal level at the output of the analogue routing block should not exceed +8.69db, assuming both fine and coarse output le v el adjustments are set to 0db. the sub - audio level is normally set to 31mvrms 1.0db, which means that the output from the soft limiter must not exceed 803mv rms. if pre - emphasis is used, an output signal at 3000hz will have three times the amplitude of a signal at 1000hz, so the signal level before pre - emphasis should not exceed 268mvrms. if the compressor is also used, its knee is at 100mvrms, which would allow a signal into the compressor of 718mvrms, which is less than the maximum signal level. the f ine input level adjustment has a maximum attenuation of 3.5db and no gain, whereas the coarse input level adjustment has a variable gain of up to +22.4db and no attenuation. if the highest gain setting were used, then the maximum allowable input signal lev el at the micfb pin would be 54mvrms. with the lowest gain setting (0db), the maximum allowable input signal level at the micfb pin would be 718mvrms. 7.19.2 receive path levels for the maximum signal output from the audio gain/attenuator stage, the signal level at the output of the analogue routing block should not exceed +8.69db, assuming both fine and coarse output level adjustments are set to 0db. in this case, there is no sub - audio signal to be added, so the maximum signal level remains at 838mvrms. if de - e mphasis is used, an output signal at 300hz will have three and a third times the amplitude of a signal at 1000hz, so the signal level before de - emphasis should not exceed 251mvrms. if the expander is also used, its knee is at 100mvrms, which would allow a signal into the expander of 158mvrms. the fine input level adjustment has a maximum attenuation of 3.5db and no gain, whereas the coarse input level adjustment has a variable gain of up to +22.4db and no attenuation. if the highest gain setting were use d, then the maximum allowable input signal level at the discfb pin would be 12.0mv rms. with the lowest gain setting (0db), the maximum allowable input signal level at the discfb pin would be 158mvrms. the signal level of +8.69db (838mvrms) is an absolute maximum, which should not be exceeded anywhere in the signal processing chain if severe distortion is to be avoided. in - band tones msk / ffsk / audio tones sub - audio processing voice processing mux $ b 1 : b 5 - 2 mux $ c 1 : b 15 - 2 mux $ a 7 : b 15 - 12 $ c 1 : b 15 - 2 mux $ b 1 : b 9 - 6 audio mod 1 mod 2 discn altn micn input 1 input 2 output 1 output 2 fine gain : $ cd : 110 x fine gain : $ cd : 110 x coarse gain : $ b 0 : b 14 - 12 coarse gain : $ b 0 : b 10 - 8 coarse gain : $ b 0 : b 3 - 0 fine gain : p 4 . 2 or $ cd : 011 x offset : p 4 . 4 fine gain : p 4 . 3 or $ cd : 100 x offset : p 4 . 5 tone level : $ cd : 001 x or p 1 . 0 rx voice level : $ cd : 010 x level : p 2 . 0 fine gain : p 4 . 0 fine gain : p 4 . 1 input 2 gain : $ b 1 : b 15 - 13 input 1 gain : $ b 1 : b 12 - 10 note : with fi - 1 . 3 . 8 . 2 onwards : rx voice level adjust ( $ cd : 010 x ) is only active in rx mode tx mult ( $ cd : 101 x ) is only active in tx mode tx mult x 2 , x 4 , x 8 : $ cd : 101 x
the two - way radio processor CMX7031/cmx7041 ? 7.20. c - bus register summary table 14 c - bus registers addr. (hex) register word size (bits) $01 w c - bus reset 0 $a7 w auxadc and tx mod mode 16 $a8 w auxdac control/data 16 $a9 r auxadc1 data/checksum 2 hi 16 $aa r auxadc2 data/checksum 2 lo 16 $ab w sysclk1 pll data 16 $ac w sysclk1 ref 16 $ad w sysclk2 pll data 16 $ae w sysclk2 ref 16 $af reserved $b0 w analogue output gain 16 $b1 w input gain and output signal routing 16 $b2 w rf channel data 16 $b3 w rf channel control 16 $b4 r rf channel status 8 $b5 w auxadc threshold data 16 $b6 w modem rx address 16 $b7 reserved $b8 r checksum 1 hi 16 $b9 r checksum 1 lo 16 $ba reserved $bb r nwr status and data 16 $bc reserved $bd reserved $be reserved $bf reserved $c0 w power - down control 16 $c1 w mode control 16 $c2 w audio control 16 $c3 w tx inband tones 16 $c4 re served $c5 r rx data 1 16 $c6 r status 16 $c7 w modem control 16 $c8 w programming 16 $c9 r rx data 2 and xtcss 16 $ca w tx data 1 16 $cb w tx data 2 and xtcss 16 $cc r tone status 16 $cd w audio tone 16 $ce w interrupt mask 16 $cf reserved all other c - bus addresses (including those not listed above) are either reserved for future use or allocated for production testing and must not be accessed in normal operation.
the two - way radio processor CMX7031/cmx7041 ? 7.20.1 interrupt operation the CMX7031/cmx7041 will issue an interrupt on the irqn line when the irq bit (bit 15) of the status register and the irq mask bit (bit 15) are both set to 1. the irq bit is set when the state of the interrupt flag bits in the status register change from a 0 to 1 and the corresponding mask bit(s) in the interr upt mask register is(are) set. enabling an interrupt by setting a mask bit (0 ? 1) after the corresponding status register bit has already been set to 1 will also cause the irq bit to be set. all interrupt flag bits in the status register, except the program ming flag (bit 0) and the rf channel status flag (bit 1), are cleared and the interrupt request is cleared following the command/address phase of a c - bus read of the status register. the programming flag bit is set to 1 only when it is permissible to writ e a new word to the programming register. see: o status C $c6 read o interrupt mask C $ce write 7.20.2 general notes in normal operation, the most significant registers are: o mode control C $c1 write o status C $c6 read o analogue output gain C $b0 write o input gain and output signal routing C $b1 write o audio control C $c2 write setting the mod e register to either rx or tx will automatically increase the internal clock speed to its operational speed, whilst setting the mode register to idle will automatically return the internal clock to a lower (powersaving) speed. to access the program blocks (through the programming register, $c8) t he device must be in idle mode. under normal circumstances the CMX7031/cmx7041 manages the main clock control automatically, using the default values loaded in program block 3.
the two - way radio processor CMX7031/cmx7041 ? 8. performance specification 8.1. electrical performance 8.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. unit supply: dv dd - dv ss ? dd - av ss ? dd - rfv ss ? dd - rfv ss ? ss ? dd + 0.3 v voltage on any pin to av ss ? dd + 0.3 v voltage on any pin to rfv ss (excluding cpv dd ) ? dd + 0.3 v current into or out of any power supply pin (excluding v bias ) (i.e. v dec , av dd , av ss , dv dd , dv ss , cpv dd, rfv dd or rfv ss) ? ? dd and av dd or cpv dd 0 0.3 v av dd and cpv dd 0 0.3 v dv ss and av ss or rfv ss 0 50 mv av ss and rfv ss 0 50 mv l9 package (64 - pi n lqfp) min. max. unit total allowable power dissipation at tamb = 25c C 1690 mw derating C 16.9 mw/c storage temperature ? 55 +125 c operating temperature ? 40 +85 c q1 package (64 - pin vqfn) min. max. unit total allowable power dissipation at tamb = 25c C 3500 mw derating C 35.0 mw/c storage temperature ? 55 +125 c operating temperature ? 40 +85 c l4 package (48 - pin lqfp) min. max. unit total allowable power dissipation at tamb = 25c C C ? ? q3 package (48 - pin vqfn) min. max. unit total allowable power dissipation at tamb = 25c C 1750 mw ... derating C 17.5 mw/c storage temperature ? 55 +125 c operating temperature ? 40 +85 c
the two - way radio processor CMX7031/cmx7041 ? 8.1.2 operating limits correct operation of the device outside these limits is not implied. notes min. max. unit supply voltage: dv dd C ss 3.0 3.6 v av dd C ss 3.0 3.6 v cpv dd C ss 3.0 3.6 v rfv dd C ss 13 2.25 2.75 v v dec C ss 12 2.25 2.75 v operating temperature ? notes: 11 nominal xtal/c lk frequency is 6.144mhz. 12 the v dec supply is automatically created from dv dd by the on - chip voltage regulator. 13 the rfv dd supply can be supplied from the v dec supply, if preferred.
the two - way radio processor CMX7031/cmx7041 ? 8.1.3 operating characteristics for the following conditions unless otherwise specified: external components as recommended in figure 2 . maximum load on digital outputs = 30pf. xtal frequency = 6.144mhz ? 0.01% (100ppm); tamb = ? 40c to +85c. av dd = dv dd = cpv dd = 3.0v to 3.6v; rfv dd = 2.25v to 2.75v. reference signal level = 308mvrms at 1khz with av dd = 3.3v. signal levels track with supply voltage, so scale accordingly. signal to noise ratio (snr) in bit rate bandwidth. input stage gain = 0db. output stage attenuation = 0db. cur rent consumption figures quoted in this section apply to the device when loaded with fi 1. 5 only. the use of other function images ? , can modify the current consumption of the device. dc parameters notes min. typ. max. unit supply current 21 all powersaved di dd (dv dd = 3.3v, v dec = 2.5v) C 50 100 a ai dd (av dd = 3.3v) C 4 20 a cpi dd + rfi dd (cpv dd = 3.3v, rfv dd = 2.5v) C 4 20 a idle mode 22 di dd (dv dd = 3.3v, v dec = 2.5v) C 1.1 C ma ai dd (av dd = 3.3v) C 250 C a rx mode 22 di dd (dv dd = 3.3v, v dec = 2.5v) C 4.8 C ma ai dd (av dd = 3.3v) C 3.0 C ma tx mode 22 di dd (dv dd = 3.3v, v dec = 2.5v) C 6.1 C ma ai dd (av dd = 3.3v) C 3.0 C ma additional current for each rf synthesiser 23 cpi dd + rfi dd (cp v dd = 3.3v, rfv dd = 2.5v) C 2.5 4.5 ma additional current for each auxiliary system clock (output running at 4mhz) di dd (dv dd = 3.3v, v dec = 2.5v) C 500 C a additional current for each auxiliary adc di dd (dv dd = 3.3v, v dec = 2.5v) C 5 C a additional current for each auxiliary dac ai dd (av dd = 3.3v) C 200 C a notes: 21 tamb = 25c, not including any current drawn from the device pins by external circuitry. 22 system clocks, rf, auxiliary circuits, audio scrambler , co mpander and pre/de - emphasis disabled, but all other digital circuits (including the main clock pll) enabled. a single analogue path is enabled through the device. 23 when using the external components shown in figure 24 and when supplying the current for rfv dd from the regulated 2.5v digital (v dec ) supply. the latter is derived from dv dd by an on - chip voltage regulator.
the two - way radio processor CMX7031/cmx7041 ? dc parameters (continued) notes min. typ. max. unit xtal/clk 25 input logic 1 C C dd input logic 0 C C dd input current (vin = dv dd ) C C ss ) ? C C c - bus interface and logic inputs input logic 1 C C dd input logic 0 C C dd input leakage current (logic 1 or 0) ? C C C c - bus interface and logic outputs output logic 1 oh = 120a) 90% C C dd (i oh = 1ma) 80% C C dd output logic 0 ol = 360a) C C dd (i ol = - 1.5ma) C C dd off state leakage current C C dd ) ? C ? C v bias 26 output voltage offset wrt av dd /2 (i ol < 1 ? C C dd output impedance C C ? notes: 25 characteristics when driving the xtal/clk pin with an external clock source. 26 applies when utilising v bias to provide a reference voltage to other parts of the system. when using v bias as a reference, v bias must be buffered. v bias must always be deco upled with a capacitor as shown in figure 2 .
the two - way radio processor CMX7031/cmx7041 ? a c parameters notes min. typ. max. unit xtal/clk input high pulse width C C low pulse width C C C C ? C C C C ? C C C C auxiliary sysclk1/2 outputs xtal/clk input to clock_out timing: (in high to out high) 32 C C C C high pulse width low pulse width v bias start - up time (from powersave) C C microphone, alternative and discrim inator inputs (mic, alt, disc) input impedance 34 C C ? C C dd load resistance (feedback pins) 80 C C ? ? ? C C C C programmable input gain stage 36 gain (at 0db) 37 ? ? ? ? notes: 31 timing for an external input to the xtal/clk pin. 32 xtal/clk input driven by an external source. 33 6.144mhz xtal fitted and 6.144mhz output selected. 34 with no external components connected. 35 centred about av dd /2; after multiplying by the gain of input circuit (with external components connected). 36 gain applied to signal at output of buffer amplifier: discfb, altfb or micfb. 37 design value. overall attenuation input to output has a tolerance of 0db 1.0db.
the two - way radio processor CMX7031/cmx7041 ? a c parameters notes min. typ. max. unit modulator outputs 1/2 and audio output (mod 1, mod 2, audio) power - up to outputs stable 41 C modulator attenuators attenuation (at 0db) 43 ? ? ? ? ? C C ? ? C C ? dd = 3.3v) C C C dd C C C ? audio attenuator attenuation (at 0db) 43 ? ? ? ? ? C C ? ? C C ? dd = 3.3v) C C C dd C C C ? notes: 41 power - up refers to issuin g a c - bus command to turn on an output. these limits apply only if v bias is on and stable. at power supply switch - on, the default state is for all blocks, except the xtal and c - bus interface, to be in placed in powersave mode. 42 small signal impedance , at av dd = 3.3v and tamb = 25c. 43 with respect to the signal at the feedback pin of the selected input port. 44 centred about av dd /2; with respect to the output driving a 20k ? dd /2.
the two - way radio processor CMX7031/cmx7041 ? a c parameters (cont.) notes min. typ. max. unit auxiliary signal inputs (aux adc 1 to 4) source output impedance 51 C C ? auxiliary 10 bit adcs resolution C C C C dd conversion time 52 C C C C ? C C ? ? C C C C C auxiliary 10 bit dacs resolution C C C C dd zero error ? ? C C C ? C C C C notes: 51 denotes output im pedance of the driver of the auxiliary input signal, to ensure < 1 bit additional error under nominal conditions. 52 with an auxiliary clock frequency of 6.144mhz. 53 guaranteed monotonic with no missing codes. 54 centred about av dd /2.
the two - way radio processor CMX7031/cmx7041 ? a c par ameters (cont.) notes min. typ. max. unit rf synthesisers C phase locked loops reference clock input input logic 1 C C dd input logic 0 C C dd frequency 64,66 5.0 19.2 40.0 mhz divide ratios (r) 63 2 C each rf synthesiser 69 comparison frequency C C C ? C C C C C ? C ? ? ? ? ? ? C C C C C C notes: 62 square wave input. 63 separate dividers are provided for each pll. 64 for optimum performance of the s ynthesiser subsystems, a common master clock should be used for the rf s ynthesiser s and the baseband sections. using unsynchronised clocks is likely to result in spurious products being generated in the synthesiser outputs and in some cases difficulty may be experienced in obtaining lock in the rf synthesisers. 65 external iset resistor (r31) = 0 (internal iset resistor = 9k6 nominally). 10 (n) + 10log 10 (f comparison ) 69 it is recommended that rf synthesiser 1 be used for the higher frequency use (eg: rf 1 st lo) and rf synthesiser 2 be used for lower frequency use (eg: if lo).
the two - way radio processor CMX7031/cmx7041 ? 8.1.4 parametric performance for the following conditions unless otherwise specified: external components as recommended in figure 2 . maximum load on digital outputs = 30pf. xtal frequency = 6.144mhz ? 0.003% (30ppm) ; tamb = ? 40c to +85c. av dd = dv dd = cpv dd = 3.0v to 3.6v; rfv dd = 2.25v to 2.75v. reference signal level = 308mvrms at 1khz with av dd = 3.3v. signal levels track with supp ly voltage, so scale accordingly. signal to noise ratio (snr) in bit rate bandwidth. input stage gain = 0db, output stage attenuation = 0db. all figures quoted in this section apply to the device when loaded with fi 1. 5 only. the use of other function ima ges ? , can modify the parametric performance of the device. a c parameters (cont.) notes min. typ. max. unit receiver signal type identification probability of correctly identifying signal type (snr = 12db) C >>99.9 C % ctcss detector sensitivity (pure tone) 71 C ? 26 C db sinad opening 72 C 5 C db response time (composite signal) 72 C 225 250 ms de - response time (composite signal) 72, 75 C 210 250 ms dropout immunity 75 C 160 C ms falsing 72 C 1 C frequency ran ge 60 C 260 hz inband tone detector sensitivity (pure tone) 73 C ? 26 C db response time (good signal) C 35 C ms de - response time (good signal) C C 45 ms drop - out immunity 76 C C 20 ms frequency range (inband tone) 288 C 3000 hz dcs decoder sensitivity 71 44 C C mvp - p bit - rate sync time C 2 C edges msk/ffsk decoder signal input dynamic range 74 100 C 800 mvrms bit error rate (snr = 20db) 74 C <1 C 10 - 8 receiver synchronisation (snr = 12db) probability of bit 16 being correct C >99.9 C % fsk/dsc decoder signal input dynamic range 74 100 C 800 mvrms bit error rate (snr = 8db) 74 C <1 C 10 - 2 co - channel rejection C 10 C db
the two - way radio processor CMX7031/cmx7041 ? notes: to meet dsc specifications, a 30ppm xtal, or better, is required. 71 sub - audio detection level threshold set to 16mvrms (ctcss) or 44mvpk - pk (dcs). 72 tested as per tia - 603 c. 73 inband tone detection level threshold set to 16mv. 74 av dd = 3.3v, for a 101010101 01 patter dd . 75 with sub - audio dropout time (p2.5) set to default. the typical dropout immunity is approximately 40ms more than the programmed dropout time. the typical de - response time is approximately 90ms longer than the programmed dropout time. see section 9.2.3 , p2.5 in the CMX7031/cmx7041 user manual. 76 immunity to signal drop - outs of up to the specified duration.
the two - way radio processor CMX7031/cmx7041 ? a c parameters (cont.) notes min . typ. max. unit dtmf decoder sensitivity C C C C C C C C C C nwr decoder sensitivity C C audio compandor attack time C C C C C C C C ctcss encoder frequency range 60.0 C C C ? C inband tone encoder frequency range 288 C C C ? C dcs encoder bit rate C C ? dtmf encoder output signal level (2db twist) C C C msk/ffsk e ncoder output signal level C C ? C C rd harmonic distortion C C C C psk encoder bit rate C C C C
the two - way radio processor CMX7031/cmx7041 ? notes: 81 av dd = 3.3v and tx sub - audio level set to 88mv p - p (31mvrms). 82 measured at mod 1 or mod 2 output. 83 av dd = 3.3v and tx audio level set to 871mv p - p (308mvrms). 84 av dd = 3.3v.
the two - way radio processor CMX7031/cmx7041 ? a c parameters (cont.) notes min. typ. max. unit fsk/dsc encoder output signal level C C C C rd harmonic distortion C C C C C C C C C C analogue channel audio filtering pass - band (nominal bandwidth): recei ved audio 91 300 C C C C C ? C C C ? C C ? C C C C ? C audio scrambler inversion frequency C C C audi o expandor input signal range 97 C C notes: 91 the receiver audio filter complies with the characteristic shown in figur e 10 . the high pass filtering removes sub - audio components from the audio sign al. 9 2 the 12.5khz channel filter complies with the characteristic shown in figure 14 . 93 the 25khz channel filter complies with the characteristic shown in figure 13 . 94 the pre - emphasis filter complies w ith the characteristic shown in fi gure 15 95 the de - emphasis filter complies with the characteristic shown in figure 12 . 96 psophometrically weighted. pre/de - emphasis, compandor and 25khz channel filter selected. 97 av dd = 3.3v.
the two - way radio processor CMX7031/cmx7041 ? 8.2. c - bus timing figure 28 c - bus timing c - bus timing notes min. typ. max. unit t cse csn enable to sclk high time 100 C C csh last sclk high to csn high time 100 C C loz sclk low t o rdata output enable time 0.0 C C hiz csn high to rdata high impedance C C csoff csn high time between transactions 1.0 C C nxt inter - byte time 200 C C ck sclk cycle time 200 C C ch sclk high time 100 C C cl sclk lo w time 100 C C cds cdata setup time 75 C C cdh cdata hold time 25 C C rds rdata setup time 50 C C rdh rdata hold time 0 C C notes: 1. depending on the command, 1 or 2 bytes of cdata are transmitted to the peripheral ms b (bit 7) first, lsb (bit 0) last. rdata is read from the peripheral msb (bit 7) first, lsb (bit 0) last. 2. data is clocked into the peripheral on the rising sclk edge. 3. commands are acted upon at the end of each command (rising edge of csn). 4. to allow for differing c serial interface formats c - bus compatible ics are able to work with sclk pulses starting and ending at either polarity. 5. maximum 30pf load on irqn pin and each c - bus interface line. these timings are for the latest version of c - b us and allow faster transfers than the origin al c - bus timing specification. the CMX7031/cmx7041 can be used in conjunction with devices that comply with the slower timings, subject to system throughput constraints.
the two - way radio processor CMX7031/cmx7041 ? 8.3. packaging figure 29 mechanical outline of 64 - pin vqfn (q1) order as part no. CMX7031q1 figure 30 mechanical outline of 64 - pin lqfp (l9) order as part no. CMX7031l9 a b c h typ. max. min. dim. j p t 1.00 0.80 0.05 0.30 0.50 0.00 0.20 0.18 9.00 bsc 9.00 bsc * * note : * all dimensions in mm angles are in degrees a & b are reference data and do not include mold deflash or protrusions. f 7.80 7.00 g 7.80 7.00 l 0.50 0.30 index area 1 dot index area 2 dot chamfer index area 1 is located directly above index area 2 depending on the method of lead termination at the edge of the package, pull back (l1) may be present. l minus l1 to be equal to, or greater than 0.3mm the underside of the package has an exposed metal pad which should ideally be soldered to the pcb to enhance the thermal conductivity and mechanical strength of the package fixing. where advised, an electrical connection to this metal pad may also be required l1 0.15 0 k 0.20 0.90 0.25 0.40 exposed metal pad
the two - way radio processor CMX7031/cmx7041 ? figure 31 mechanical outline of 48 - pin vqfn (q 3) order as part no. cmx7041q3 figure 32 mechanical outline of 48 - pin lqfp (l4) order as part no. cmx7041l4 as package dimensions may change after publication of this datasheet, it is recommended that you check for the lates t packaging information from the design support area of the cml website: [ http://www.cmlmicro.com/ ]. depending on the method of lead termination at the edge of the package, pull back (l1) may be present. l minus l1 to be equal to, or greater than 0.3mm the underside of the package has an exposed metal pad which should ideally be soldered to the pcb to enhance the thermal conductivity and mechanical strength of the package fixing. where advised, an electrical connection to this metal pad may also be required a b c h typ. max. min. dim. j 1.00 0.80 0.05 0.30 0.00 0.18 7.00 bsc 7.00 bsc * * note : * all dimensions in mm angles are in degrees a & b are reference data and do not include mold deflash or protrusions. f 5.65 4.60 g 5.65 4.60 l 0.50 0.30 index area 1 dot index area 2 dot chamfer index area 1 is located directly above index area 2 p t 0.50 0.20 l1 0.15 0 exposed metal pad k 0.20 0.90 0.25 0.40
the two - way radio processor CMX7031/cmx7041 ? about firmasic ? cmls proprietary firmasic ? component technology reduces cost, tim e to market and development risk, with increased flexibility for the designer and end application. firmasic ? combines analogue, digital, firmware and memory technologies in a single silicon platform that can be focused to deliver the right feature mix, pe rformance and price for a target application family. specific functions of a firmasic ? device are determined by uploading its function image? during device initialization. new function images? may be later provided to supplement and enhance device funct ions, expanding or modifying end - product features without the need for expensive and time - consuming design changes. firmasic ? devices provide significant time to market and commercial benefits over custom asic, structured asic, fpga and dsp solutions. the y may also be exclusively customised where security or intellectual property issues prevent the use of application specific standard products (assps). handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro - static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circuit patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. specific testing of all circuit parameters is not necessarily performed .

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